Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T7,T13,T22
1	0	Covered	T5,T13,T22

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56755701	9021	0	0
CascadeEffAonToRstPorAboveRise_A	56755701	9021	0	0
CascadeEffAonToRstPorIoAboveFall_A	54484167	9021	0	0
CascadeEffAonToRstPorIoAboveRise_A	54484167	9021	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27242879	9021	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27242879	9021	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13621056	9021	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13621056	9021	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27242985	9021	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27242985	9021	0	0
CascadeLcToLcAboveFall_A	56755701	22516	0	0
CascadeLcToLcAboveRise_A	56755701	22516	0	0
CascadeLcToLcAonAboveFall_A	1719911	22516	0	0
CascadeLcToLcAonAboveRise_A	1719911	22516	0	0
CascadeLcToLcShadowedAboveFall_A	56755701	22516	0	0
CascadeLcToLcShadowedAboveRise_A	56755701	22516	0	0
CascadePorToAonAboveFall_A	1719911	7088	0	0
CascadeSysToSysAboveFall_A	56755701	22516	0	0
CascadeSysToSysAboveRise_A	56755701	22516	0	0
ScanRstToAonRise_A	1719911	218	0	0
StablePorToAonRise_A	1719911	9021	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12175505	22516	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12175505	22516	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12175505	22516	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12175505	22516	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13621056	22516	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13621056	22516	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12175505	22516	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12175505	22516	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12175505	22516	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12175505	22516	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	9021	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	27	0	0
T4	23756	2	0	0
T5	117372	9	0	0
T6	18345	2	0	0
T7	18505	2	0	0
T8	19039	2	0	0
T9	7650	1	0	0
T10	216577	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	9021	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	27	0	0
T4	23756	2	0	0
T5	117372	9	0	0
T6	18345	2	0	0
T7	18505	2	0	0
T8	19039	2	0	0
T9	7650	1	0	0
T10	216577	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54484167	9021	0	0
T1	7782	2	0	0
T2	11097	1	0	0
T3	116912	27	0	0
T4	22806	2	0	0
T5	112639	9	0	0
T6	17611	2	0	0
T7	17760	2	0	0
T8	18278	2	0	0
T9	7344	1	0	0
T10	207886	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54484167	9021	0	0
T1	7782	2	0	0
T2	11097	1	0	0
T3	116912	27	0	0
T4	22806	2	0	0
T5	112639	9	0	0
T6	17611	2	0	0
T7	17760	2	0	0
T8	18278	2	0	0
T9	7344	1	0	0
T10	207886	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242879	9021	0	0
T1	3890	2	0	0
T2	5549	1	0	0
T3	58451	27	0	0
T4	11402	2	0	0
T5	56335	9	0	0
T6	8805	2	0	0
T7	8882	2	0	0
T8	9139	2	0	0
T9	3671	1	0	0
T10	103962	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242879	9021	0	0
T1	3890	2	0	0
T2	5549	1	0	0
T3	58451	27	0	0
T4	11402	2	0	0
T5	56335	9	0	0
T6	8805	2	0	0
T7	8882	2	0	0
T8	9139	2	0	0
T9	3671	1	0	0
T10	103962	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	9021	0	0
T1	1944	2	0	0
T2	2772	1	0	0
T3	29231	27	0	0
T4	5700	2	0	0
T5	28167	9	0	0
T6	4403	2	0	0
T7	4439	2	0	0
T8	4569	2	0	0
T9	1835	1	0	0
T10	51963	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	9021	0	0
T1	1944	2	0	0
T2	2772	1	0	0
T3	29231	27	0	0
T4	5700	2	0	0
T5	28167	9	0	0
T6	4403	2	0	0
T7	4439	2	0	0
T8	4569	2	0	0
T9	1835	1	0	0
T10	51963	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242985	9021	0	0
T1	3890	2	0	0
T2	5548	1	0	0
T3	58474	27	0	0
T4	11402	2	0	0
T5	56327	9	0	0
T6	8802	2	0	0
T7	8881	2	0	0
T8	9136	2	0	0
T9	3671	1	0	0
T10	103972	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242985	9021	0	0
T1	3890	2	0	0
T2	5548	1	0	0
T3	58474	27	0	0
T4	11402	2	0	0
T5	56327	9	0	0
T6	8802	2	0	0
T7	8881	2	0	0
T8	9136	2	0	0
T9	3671	1	0	0
T10	103972	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	22516	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	102	0	0
T4	23756	2	0	0
T5	117372	53	0	0
T6	18345	6	0	0
T7	18505	6	0	0
T8	19039	6	0	0
T9	7650	1	0	0
T10	216577	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	22516	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	102	0	0
T4	23756	2	0	0
T5	117372	53	0	0
T6	18345	6	0	0
T7	18505	6	0	0
T8	19039	6	0	0
T9	7650	1	0	0
T10	216577	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	22516	0	0
T1	242	2	0	0
T2	346	1	0	0
T3	3669	102	0	0
T4	711	2	0	0
T5	3619	53	0	0
T6	549	6	0	0
T7	553	6	0	0
T8	569	6	0	0
T9	229	1	0	0
T10	6511	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	22516	0	0
T1	242	2	0	0
T2	346	1	0	0
T3	3669	102	0	0
T4	711	2	0	0
T5	3619	53	0	0
T6	549	6	0	0
T7	553	6	0	0
T8	569	6	0	0
T9	229	1	0	0
T10	6511	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	22516	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	102	0	0
T4	23756	2	0	0
T5	117372	53	0	0
T6	18345	6	0	0
T7	18505	6	0	0
T8	19039	6	0	0
T9	7650	1	0	0
T10	216577	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	22516	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	102	0	0
T4	23756	2	0	0
T5	117372	53	0	0
T6	18345	6	0	0
T7	18505	6	0	0
T8	19039	6	0	0
T9	7650	1	0	0
T10	216577	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	7088	0	0
T1	242	2	0	0
T2	346	1	0	0
T3	3669	27	0	0
T4	711	18	0	0
T5	3619	5	0	0
T6	549	1	0	0
T7	553	1	0	0
T8	569	1	0	0
T9	229	1	0	0
T10	6511	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	22516	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	102	0	0
T4	23756	2	0	0
T5	117372	53	0	0
T6	18345	6	0	0
T7	18505	6	0	0
T8	19039	6	0	0
T9	7650	1	0	0
T10	216577	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56755701	22516	0	0
T1	8105	2	0	0
T2	11559	1	0	0
T3	121806	102	0	0
T4	23756	2	0	0
T5	117372	53	0	0
T6	18345	6	0	0
T7	18505	6	0	0
T8	19039	6	0	0
T9	7650	1	0	0
T10	216577	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	218	0	0
T22	24708	4	0	0
T23	5707	1	0	0
T34	0	4	0	0
T48	435	0	0	0
T49	735	0	0	0
T50	729	0	0	0
T51	730	0	0	0
T52	731	0	0	0
T74	210	0	0	0
T87	20186	6	0	0
T88	0	6	0	0
T90	0	5	0	0
T95	0	9	0	0
T104	0	1	0	0
T106	731	0	0	0
T107	0	5	0	0
T110	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	9021	0	0
T1	242	2	0	0
T2	346	1	0	0
T3	3669	27	0	0
T4	711	2	0	0
T5	3619	9	0	0
T6	549	2	0	0
T7	553	2	0	0
T8	569	2	0	0
T9	229	1	0	0
T10	6511	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	22516	0	0
T1	1944	2	0	0
T2	2772	1	0	0
T3	29231	102	0	0
T4	5700	2	0	0
T5	28167	53	0	0
T6	4403	6	0	0
T7	4439	6	0	0
T8	4569	6	0	0
T9	1835	1	0	0
T10	51963	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	22516	0	0
T1	1944	2	0	0
T2	2772	1	0	0
T3	29231	102	0	0
T4	5700	2	0	0
T5	28167	53	0	0
T6	4403	6	0	0
T7	4439	6	0	0
T8	4569	6	0	0
T9	1835	1	0	0
T10	51963	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12175505	22516	0	0
T1	1854	2	0	0
T2	2707	1	0	0
T3	25837	102	0	0
T4	5538	2	0	0
T5	23751	53	0	0
T6	4163	6	0	0
T7	4200	6	0	0
T8	4326	6	0	0
T9	1745	1	0	0
T10	49151	102	0	0