Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T11,T22
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T11
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13621056	14439	0	0
gen_assertions[0].RstEnOn_A	13621056	1086	0	0
gen_assertions[0].RstNOff_A	13621056	14439	0	0
gen_assertions[0].RstNOn_A	13621056	1086	0	0
gen_assertions[1].RstEnOff_A	54484167	13159	0	0
gen_assertions[1].RstEnOn_A	54484167	1064	0	0
gen_assertions[1].RstNOff_A	54484167	13159	0	0
gen_assertions[1].RstNOn_A	54484167	1064	0	0
gen_assertions[2].RstEnOff_A	27242879	13228	0	0
gen_assertions[2].RstEnOn_A	27242879	1089	0	0
gen_assertions[2].RstNOff_A	27242879	13228	0	0
gen_assertions[2].RstNOn_A	27242879	1089	0	0
gen_assertions[3].RstEnOff_A	27242985	13254	0	0
gen_assertions[3].RstEnOn_A	27242985	1111	0	0
gen_assertions[3].RstNOff_A	27242985	13254	0	0
gen_assertions[3].RstNOn_A	27242985	1111	0	0
gen_assertions[4].RstEnOff_A	1719911	22396	0	0
gen_assertions[4].RstEnOn_A	1719911	1160	0	0
gen_assertions[4].RstNOff_A	1719911	22396	0	0
gen_assertions[4].RstNOn_A	1719911	1160	0	0
gen_assertions[5].RstEnOff_A	13621056	14663	0	0
gen_assertions[5].RstEnOn_A	13621056	1206	0	0
gen_assertions[5].RstNOff_A	13621056	14663	0	0
gen_assertions[5].RstNOn_A	13621056	1206	0	0
gen_assertions[6].RstEnOff_A	13621056	14716	0	0
gen_assertions[6].RstEnOn_A	13621056	1258	0	0
gen_assertions[6].RstNOff_A	13621056	14716	0	0
gen_assertions[6].RstNOn_A	13621056	1258	0	0
gen_assertions[7].RstEnOff_A	13621056	14784	0	0
gen_assertions[7].RstEnOn_A	13621056	1320	0	0
gen_assertions[7].RstNOff_A	13621056	14784	0	0
gen_assertions[7].RstNOn_A	13621056	1320	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14439	0	0
T2	2772	2	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	5	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	0	0	0
T12	0	2	0	0
T13	0	31	0	0
T22	0	172	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1086	0	0
T2	2772	2	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	1	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	0	0	0
T22	0	19	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	0	1	0	0
T87	0	41	0	0
T88	0	5	0	0
T89	0	3	0	0
T90	0	22	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14439	0	0
T2	2772	2	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	5	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	0	0	0
T12	0	2	0	0
T13	0	31	0	0
T22	0	172	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1086	0	0
T2	2772	2	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	1	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	0	0	0
T22	0	19	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	0	1	0	0
T87	0	41	0	0
T88	0	5	0	0
T89	0	3	0	0
T90	0	22	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54484167	13159	0	0
T2	11097	2	0	0
T3	116912	67	0	0
T4	22806	0	0	0
T5	112639	38	0	0
T6	17611	4	0	0
T7	17760	4	0	0
T8	18278	4	0	0
T9	7344	0	0	0
T10	207886	63	0	0
T11	24745	2	0	0
T12	0	1	0	0
T13	0	30	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54484167	1064	0	0
T2	11097	2	0	0
T3	116912	0	0	0
T4	22806	0	0	0
T5	112639	0	0	0
T6	17611	0	0	0
T7	17760	0	0	0
T8	18278	0	0	0
T9	7344	0	0	0
T10	207886	0	0	0
T11	24745	2	0	0
T22	0	24	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	0	2	0	0
T87	0	38	0	0
T88	0	5	0	0
T89	0	3	0	0
T90	0	21	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54484167	13159	0	0
T2	11097	2	0	0
T3	116912	67	0	0
T4	22806	0	0	0
T5	112639	38	0	0
T6	17611	4	0	0
T7	17760	4	0	0
T8	18278	4	0	0
T9	7344	0	0	0
T10	207886	63	0	0
T11	24745	2	0	0
T12	0	1	0	0
T13	0	30	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54484167	1064	0	0
T2	11097	2	0	0
T3	116912	0	0	0
T4	22806	0	0	0
T5	112639	0	0	0
T6	17611	0	0	0
T7	17760	0	0	0
T8	18278	0	0	0
T9	7344	0	0	0
T10	207886	0	0	0
T11	24745	2	0	0
T22	0	24	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	0	2	0	0
T87	0	38	0	0
T88	0	5	0	0
T89	0	3	0	0
T90	0	21	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242879	13228	0	0
T2	5549	3	0	0
T3	58451	67	0	0
T4	11402	0	0	0
T5	56335	38	0	0
T6	8805	4	0	0
T7	8882	4	0	0
T8	9139	4	0	0
T9	3671	0	0	0
T10	103962	63	0	0
T11	12371	3	0	0
T12	0	1	0	0
T13	0	30	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242879	1089	0	0
T2	5549	3	0	0
T3	58451	0	0	0
T4	11402	0	0	0
T5	56335	0	0	0
T6	8805	0	0	0
T7	8882	0	0	0
T8	9139	0	0	0
T9	3671	0	0	0
T10	103962	0	0	0
T11	12371	3	0	0
T22	0	25	0	0
T49	0	3	0	0
T87	0	33	0	0
T88	0	6	0	0
T89	0	2	0	0
T90	0	23	0	0
T91	0	16	0	0
T92	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242879	13228	0	0
T2	5549	3	0	0
T3	58451	67	0	0
T4	11402	0	0	0
T5	56335	38	0	0
T6	8805	4	0	0
T7	8882	4	0	0
T8	9139	4	0	0
T9	3671	0	0	0
T10	103962	63	0	0
T11	12371	3	0	0
T12	0	1	0	0
T13	0	30	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242879	1089	0	0
T2	5549	3	0	0
T3	58451	0	0	0
T4	11402	0	0	0
T5	56335	0	0	0
T6	8805	0	0	0
T7	8882	0	0	0
T8	9139	0	0	0
T9	3671	0	0	0
T10	103962	0	0	0
T11	12371	3	0	0
T22	0	25	0	0
T49	0	3	0	0
T87	0	33	0	0
T88	0	6	0	0
T89	0	2	0	0
T90	0	23	0	0
T91	0	16	0	0
T92	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242985	13254	0	0
T2	5548	4	0	0
T3	58474	67	0	0
T4	11402	0	0	0
T5	56327	38	0	0
T6	8802	4	0	0
T7	8881	4	0	0
T8	9136	4	0	0
T9	3671	0	0	0
T10	103972	63	0	0
T11	12372	4	0	0
T12	0	1	0	0
T13	0	30	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242985	1111	0	0
T2	5548	4	0	0
T3	58474	0	0	0
T4	11402	0	0	0
T5	56327	0	0	0
T6	8802	0	0	0
T7	8881	0	0	0
T8	9136	0	0	0
T9	3671	0	0	0
T10	103972	0	0	0
T11	12372	4	0	0
T22	0	22	0	0
T35	0	1	0	0
T38	0	1	0	0
T49	0	4	0	0
T87	0	40	0	0
T88	0	5	0	0
T89	0	5	0	0
T90	0	23	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242985	13254	0	0
T2	5548	4	0	0
T3	58474	67	0	0
T4	11402	0	0	0
T5	56327	38	0	0
T6	8802	4	0	0
T7	8881	4	0	0
T8	9136	4	0	0
T9	3671	0	0	0
T10	103972	63	0	0
T11	12372	4	0	0
T12	0	1	0	0
T13	0	30	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27242985	1111	0	0
T2	5548	4	0	0
T3	58474	0	0	0
T4	11402	0	0	0
T5	56327	0	0	0
T6	8802	0	0	0
T7	8881	0	0	0
T8	9136	0	0	0
T9	3671	0	0	0
T10	103972	0	0	0
T11	12372	4	0	0
T22	0	22	0	0
T35	0	1	0	0
T38	0	1	0	0
T49	0	4	0	0
T87	0	40	0	0
T88	0	5	0	0
T89	0	5	0	0
T90	0	23	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	22396	0	0
T1	242	2	0	0
T2	346	5	0	0
T3	3669	77	0	0
T4	711	2	0	0
T5	3619	53	0	0
T6	549	6	0	0
T7	553	6	0	0
T8	569	7	0	0
T9	229	1	0	0
T10	6511	96	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	1160	0	0
T2	346	4	0	0
T3	3669	0	0	0
T4	711	0	0	0
T5	3619	0	0	0
T6	549	0	0	0
T7	553	0	0	0
T8	569	1	0	0
T9	229	0	0	0
T10	6511	0	0	0
T11	772	6	0	0
T22	0	23	0	0
T49	0	4	0	0
T87	0	44	0	0
T88	0	4	0	0
T89	0	7	0	0
T90	0	23	0	0
T91	0	16	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	22396	0	0
T1	242	2	0	0
T2	346	5	0	0
T3	3669	77	0	0
T4	711	2	0	0
T5	3619	53	0	0
T6	549	6	0	0
T7	553	6	0	0
T8	569	7	0	0
T9	229	1	0	0
T10	6511	96	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1719911	1160	0	0
T2	346	4	0	0
T3	3669	0	0	0
T4	711	0	0	0
T5	3619	0	0	0
T6	549	0	0	0
T7	553	0	0	0
T8	569	1	0	0
T9	229	0	0	0
T10	6511	0	0	0
T11	772	6	0	0
T22	0	23	0	0
T49	0	4	0	0
T87	0	44	0	0
T88	0	4	0	0
T89	0	7	0	0
T90	0	23	0	0
T91	0	16	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14663	0	0
T2	2772	6	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	4	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	7	0	0
T12	0	2	0	0
T13	0	31	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1206	0	0
T2	2772	6	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	0	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	7	0	0
T22	0	26	0	0
T35	0	1	0	0
T37	0	1	0	0
T49	0	6	0	0
T87	0	44	0	0
T88	0	3	0	0
T89	0	7	0	0
T90	0	23	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14663	0	0
T2	2772	6	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	4	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	7	0	0
T12	0	2	0	0
T13	0	31	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1206	0	0
T2	2772	6	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	0	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	7	0	0
T22	0	26	0	0
T35	0	1	0	0
T37	0	1	0	0
T49	0	6	0	0
T87	0	44	0	0
T88	0	3	0	0
T89	0	7	0	0
T90	0	23	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14716	0	0
T2	2772	7	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	4	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	7	0	0
T12	0	2	0	0
T13	0	31	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1258	0	0
T2	2772	7	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	0	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	7	0	0
T22	0	21	0	0
T49	0	7	0	0
T87	0	37	0	0
T88	0	4	0	0
T89	0	9	0	0
T90	0	25	0	0
T93	0	1	0	0
T94	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14716	0	0
T2	2772	7	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	4	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	7	0	0
T12	0	2	0	0
T13	0	31	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1258	0	0
T2	2772	7	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	0	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	7	0	0
T22	0	21	0	0
T49	0	7	0	0
T87	0	37	0	0
T88	0	4	0	0
T89	0	9	0	0
T90	0	25	0	0
T93	0	1	0	0
T94	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14784	0	0
T2	2772	9	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	5	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	7	0	0
T12	0	2	0	0
T13	0	31	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1320	0	0
T2	2772	9	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	1	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	7	0	0
T22	0	22	0	0
T49	0	8	0	0
T87	0	38	0	0
T88	0	5	0	0
T89	0	9	0	0
T90	0	26	0	0
T94	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	14784	0	0
T2	2772	9	0	0
T3	29231	75	0	0
T4	5700	0	0	0
T5	28167	44	0	0
T6	4403	4	0	0
T7	4439	4	0	0
T8	4569	5	0	0
T9	1835	0	0	0
T10	51963	75	0	0
T11	6184	7	0	0
T12	0	2	0	0
T13	0	31	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13621056	1320	0	0
T2	2772	9	0	0
T3	29231	0	0	0
T4	5700	0	0	0
T5	28167	0	0	0
T6	4403	0	0	0
T7	4439	0	0	0
T8	4569	1	0	0
T9	1835	0	0	0
T10	51963	0	0	0
T11	6184	7	0	0
T22	0	22	0	0
T49	0	8	0	0
T87	0	38	0	0
T88	0	5	0	0
T89	0	9	0	0
T90	0	26	0	0
T94	0	1	0	0