Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12931363	8847	0	0
alert_regwen_rd_A	12931363	6166	0	0
cpu_regwen_rd_A	12931363	6329	0	0
sw_rst_ctrl_n_0_rd_A	12931363	11492	0	0
sw_rst_ctrl_n_1_rd_A	12931363	11571	0	0
sw_rst_ctrl_n_2_rd_A	12931363	11482	0	0
sw_rst_ctrl_n_3_rd_A	12931363	11866	0	0
sw_rst_ctrl_n_4_rd_A	12931363	11818	0	0
sw_rst_ctrl_n_5_rd_A	12931363	11831	0	0
sw_rst_ctrl_n_6_rd_A	12931363	11440	0	0
sw_rst_ctrl_n_7_rd_A	12931363	11715	0	0
sw_rst_regwen_0_rd_A	12931363	6618	0	0
sw_rst_regwen_1_rd_A	12931363	6718	0	0
sw_rst_regwen_2_rd_A	12931363	6612	0	0
sw_rst_regwen_3_rd_A	12931363	6678	0	0
sw_rst_regwen_4_rd_A	12931363	6530	0	0
sw_rst_regwen_5_rd_A	12931363	6678	0	0
sw_rst_regwen_6_rd_A	12931363	6771	0	0
sw_rst_regwen_7_rd_A	12931363	6541	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	8847	0	0
T66	10244	2	0	0
T67	2452	3	0	0
T68	3986	155	0	0
T69	10803	694	0	0
T96	2478	8	0	0
T97	11493	2	0	0
T98	2607	166	0	0
T99	4054	496	0	0
T100	4364	13	0	0
T101	20427	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6166	0	0
T22	175611	239	0	0
T23	39486	41	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T59	0	60	0	0
T63	0	272	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	186	0	0
T90	0	379	0	0
T104	0	34	0	0
T106	5097	0	0	0
T109	0	242	0	0
T112	0	78	0	0
T130	0	160	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6329	0	0
T22	175611	249	0	0
T23	39486	69	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T59	0	37	0	0
T63	0	255	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	265	0	0
T90	0	365	0	0
T104	0	22	0	0
T106	5097	0	0	0
T109	0	218	0	0
T112	0	65	0	0
T130	0	173	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11492	0	0
T12	1941	4	0	0
T13	23836	0	0	0
T22	175611	504	0	0
T23	39486	61	0	0
T37	0	4	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	253	0	0
T89	0	123	0	0
T90	0	686	0	0
T104	0	37	0	0
T131	0	8	0	0
T132	0	103	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11571	0	0
T12	1941	12	0	0
T13	23836	0	0	0
T22	175611	544	0	0
T23	39486	65	0	0
T37	0	1	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	242	0	0
T89	0	122	0	0
T90	0	763	0	0
T104	0	20	0	0
T131	0	20	0	0
T132	0	117	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11482	0	0
T12	1941	13	0	0
T13	23836	0	0	0
T22	175611	550	0	0
T23	39486	24	0	0
T37	0	15	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	298	0	0
T89	0	92	0	0
T90	0	665	0	0
T104	0	17	0	0
T131	0	12	0	0
T132	0	114	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11866	0	0
T12	1941	5	0	0
T13	23836	0	0	0
T22	175611	573	0	0
T23	39486	44	0	0
T37	0	23	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	238	0	0
T89	0	120	0	0
T90	0	622	0	0
T104	0	30	0	0
T131	0	13	0	0
T132	0	128	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11818	0	0
T12	1941	5	0	0
T13	23836	0	0	0
T22	175611	531	0	0
T23	39486	56	0	0
T37	0	15	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	270	0	0
T89	0	109	0	0
T90	0	659	0	0
T104	0	47	0	0
T131	0	15	0	0
T132	0	132	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11831	0	0
T12	1941	8	0	0
T13	23836	0	0	0
T22	175611	532	0	0
T23	39486	49	0	0
T37	0	12	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	259	0	0
T89	0	112	0	0
T90	0	671	0	0
T104	0	28	0	0
T131	0	9	0	0
T132	0	157	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11440	0	0
T12	1941	12	0	0
T13	23836	0	0	0
T22	175611	491	0	0
T23	39486	69	0	0
T37	0	12	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	276	0	0
T89	0	113	0	0
T90	0	688	0	0
T104	0	20	0	0
T131	0	17	0	0
T132	0	153	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	11715	0	0
T12	1941	10	0	0
T13	23836	0	0	0
T22	175611	571	0	0
T23	39486	52	0	0
T37	0	16	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T88	0	205	0	0
T89	0	117	0	0
T90	0	652	0	0
T104	0	11	0	0
T131	0	12	0	0
T132	0	148	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6618	0	0
T22	175611	241	0	0
T23	39486	47	0	0
T37	0	4	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	218	0	0
T89	0	37	0	0
T90	0	398	0	0
T104	0	36	0	0
T106	5097	0	0	0
T131	0	7	0	0
T132	0	31	0	0
T133	0	8	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6718	0	0
T22	175611	268	0	0
T23	39486	45	0	0
T37	0	5	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	204	0	0
T89	0	29	0	0
T90	0	373	0	0
T104	0	32	0	0
T106	5097	0	0	0
T131	0	7	0	0
T132	0	22	0	0
T133	0	1	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6612	0	0
T22	175611	238	0	0
T23	39486	53	0	0
T37	0	1	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	254	0	0
T89	0	23	0	0
T90	0	367	0	0
T104	0	44	0	0
T106	5097	0	0	0
T131	0	6	0	0
T132	0	27	0	0
T133	0	8	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6678	0	0
T22	175611	213	0	0
T23	39486	53	0	0
T37	0	13	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	187	0	0
T89	0	29	0	0
T90	0	373	0	0
T104	0	34	0	0
T106	5097	0	0	0
T131	0	7	0	0
T132	0	39	0	0
T133	0	6	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6530	0	0
T22	175611	212	0	0
T23	39486	61	0	0
T37	0	5	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	232	0	0
T89	0	30	0	0
T90	0	371	0	0
T104	0	39	0	0
T106	5097	0	0	0
T131	0	9	0	0
T132	0	27	0	0
T133	0	8	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6678	0	0
T22	175611	217	0	0
T23	39486	47	0	0
T37	0	1	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	148	0	0
T89	0	42	0	0
T90	0	381	0	0
T104	0	38	0	0
T106	5097	0	0	0
T131	0	7	0	0
T132	0	23	0	0
T133	0	14	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6771	0	0
T22	175611	238	0	0
T23	39486	96	0	0
T37	0	5	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	279	0	0
T89	0	29	0	0
T90	0	380	0	0
T104	0	40	0	0
T106	5097	0	0	0
T131	0	5	0	0
T132	0	35	0	0
T133	0	3	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12931363	6541	0	0
T22	175611	235	0	0
T23	39486	62	0	0
T37	0	4	0	0
T48	3249	0	0	0
T49	5874	0	0	0
T50	5072	0	0	0
T51	5286	0	0	0
T52	5296	0	0	0
T74	1616	0	0	0
T87	124733	0	0	0
T88	0	205	0	0
T89	0	32	0	0
T90	0	361	0	0
T104	0	31	0	0
T106	5097	0	0	0
T131	0	13	0	0
T132	0	36	0	0
T133	0	5	0	0