Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	587647	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

354566

1

T1

8

T2

7

T3

1120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	502954	1			T1	9		T2	9		T3	1500
values[0x0]	219249	1			T1	6		T2	5		T3	857
values[0x1]	220010	1			T1	5		T2	6		T3	843

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	492775	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

449438

1

T1

11

T2

10

T3

1449

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4493	1			T4	2		T5	15		T6	1
valid_sources[0x01]	4594	1			T4	1		T5	6		T6	2
valid_sources[0x02]	3651	1			T5	9		T6	1		T8	10
valid_sources[0x03]	3152	1			T4	1		T5	15		T6	3
valid_sources[0x04]	2947	1			T4	1		T5	14		T6	2
valid_sources[0x05]	2690	1			T5	8		T8	15		T9	6
valid_sources[0x06]	3229	1			T5	8		T8	17		T9	12
valid_sources[0x07]	2758	1			T4	2		T5	9		T8	17
valid_sources[0x08]	3478	1			T4	1		T5	7		T8	14
valid_sources[0x09]	3984	1			T1	1		T4	2		T5	7
valid_sources[0x0a]	3677	1			T4	2		T5	12		T8	18
valid_sources[0x0b]	3578	1			T5	9		T8	15		T9	14
valid_sources[0x0c]	3051	1			T2	1		T4	2		T5	4
valid_sources[0x0d]	3031	1			T4	1		T5	14		T8	3
valid_sources[0x0e]	3423	1			T4	2		T5	15		T8	12
valid_sources[0x0f]	3111	1			T5	14		T6	1		T8	7
valid_sources[0x10]	3003	1			T4	1		T5	7		T6	1
valid_sources[0x11]	3691	1			T5	10		T8	18		T9	12
valid_sources[0x12]	3394	1			T1	1		T5	9		T6	2
valid_sources[0x13]	4253	1			T4	1		T5	7		T8	15
valid_sources[0x14]	3293	1			T5	10		T8	5		T9	12
valid_sources[0x15]	4092	1			T4	1		T5	5		T6	5
valid_sources[0x16]	3262	1			T4	1		T5	4		T6	2
valid_sources[0x17]	4415	1			T5	7		T6	5		T8	12
valid_sources[0x18]	3365	1			T5	15		T6	1		T7	23
valid_sources[0x19]	3366	1			T1	1		T4	1		T5	12
valid_sources[0x1a]	4018	1			T5	15		T6	2		T8	6
valid_sources[0x1b]	3186	1			T4	1		T5	7		T8	12
valid_sources[0x1c]	3571	1			T2	1		T5	10		T8	14
valid_sources[0x1d]	3196	1			T4	2		T5	17		T8	11
valid_sources[0x1e]	4043	1			T4	1		T5	9		T6	3
valid_sources[0x1f]	4049	1			T5	14		T6	2		T8	6
valid_sources[0x20]	3275	1			T4	2		T5	9		T6	3
valid_sources[0x21]	5427	1			T2	3		T4	1		T5	7
valid_sources[0x22]	3482	1			T5	9		T6	5		T8	18
valid_sources[0x23]	3611	1			T5	16		T8	9		T9	11
valid_sources[0x24]	3021	1			T5	13		T8	10		T9	17
valid_sources[0x25]	3383	1			T5	9		T6	1		T8	7
valid_sources[0x26]	5304	1			T5	7		T6	7		T7	20
valid_sources[0x27]	2978	1			T5	5		T6	1		T8	11
valid_sources[0x28]	3366	1			T5	6		T8	10		T9	10
valid_sources[0x29]	2989	1			T4	2		T5	16		T8	9
valid_sources[0x2a]	2911	1			T5	12		T6	1		T8	12
valid_sources[0x2b]	2896	1			T4	1		T5	19		T8	15
valid_sources[0x2c]	3036	1			T5	11		T6	4		T8	8
valid_sources[0x2d]	3055	1			T5	13		T8	12		T9	9
valid_sources[0x2e]	4286	1			T4	1		T5	9		T6	1
valid_sources[0x2f]	5189	1			T5	10		T8	14		T9	7
valid_sources[0x30]	3001	1			T5	2		T6	16		T8	16
valid_sources[0x31]	3169	1			T5	5		T8	10		T9	9
valid_sources[0x32]	3638	1			T1	2		T5	11		T8	5
valid_sources[0x33]	3018	1			T5	12		T8	9		T9	10
valid_sources[0x34]	3213	1			T1	2		T5	7		T6	3
valid_sources[0x35]	3020	1			T1	3		T4	2		T5	8
valid_sources[0x36]	3622	1			T5	12		T6	3		T8	12
valid_sources[0x37]	3393	1			T5	9		T8	6		T9	9
valid_sources[0x38]	3729	1			T4	1		T5	8		T6	2
valid_sources[0x39]	4108	1			T5	6		T6	1		T8	13
valid_sources[0x3a]	3852	1			T5	15		T6	2		T8	5
valid_sources[0x3b]	3306	1			T5	11		T6	4		T8	4
valid_sources[0x3c]	3147	1			T5	11		T7	3		T8	8
valid_sources[0x3d]	3081	1			T4	3		T5	16		T8	14
valid_sources[0x3e]	3433	1			T4	1		T5	17		T8	11
valid_sources[0x3f]	3059	1			T4	2		T5	11		T6	3
valid_sources[0x40]	3569	1			T4	1		T5	17		T6	8
valid_sources[0x41]	3981	1			T2	1		T4	2		T5	3
valid_sources[0x42]	3315	1			T5	17		T8	7		T9	13
valid_sources[0x43]	4196	1			T5	7		T6	1		T8	6
valid_sources[0x44]	3716	1			T5	14		T6	6		T8	15
valid_sources[0x45]	4118	1			T5	8		T8	10		T9	16
valid_sources[0x46]	3098	1			T4	1		T5	9		T7	13
valid_sources[0x47]	3379	1			T4	1		T5	14		T8	11
valid_sources[0x48]	3076	1			T5	14		T8	9		T9	8
valid_sources[0x49]	2928	1			T5	10		T8	6		T9	16
valid_sources[0x4a]	3404	1			T4	1		T5	2		T6	2
valid_sources[0x4b]	3594	1			T4	1		T5	5		T8	15
valid_sources[0x4c]	4095	1			T4	2		T5	9		T6	1
valid_sources[0x4d]	4141	1			T5	13		T6	3		T8	9
valid_sources[0x4e]	5358	1			T4	1		T5	10		T8	6
valid_sources[0x4f]	4494	1			T5	9		T6	1		T8	9
valid_sources[0x50]	3485	1			T5	5		T8	13		T9	21
valid_sources[0x51]	3171	1			T4	4		T5	8		T7	5
valid_sources[0x52]	3370	1			T5	8		T6	4		T8	4
valid_sources[0x53]	5667	1			T5	8		T8	10		T9	12
valid_sources[0x54]	2956	1			T4	1		T5	7		T6	2
valid_sources[0x55]	4415	1			T4	1		T5	13		T6	3
valid_sources[0x56]	3390	1			T5	9		T8	6		T9	13
valid_sources[0x57]	3494	1			T5	13		T8	10		T9	5
valid_sources[0x58]	3629	1			T4	2		T5	10		T6	1
valid_sources[0x59]	5495	1			T4	2		T5	14		T6	4
valid_sources[0x5a]	3769	1			T5	8		T8	7		T9	18
valid_sources[0x5b]	3247	1			T4	1		T5	4		T8	16
valid_sources[0x5c]	3995	1			T5	6		T8	11		T9	9
valid_sources[0x5d]	4231	1			T5	8		T6	2		T8	10
valid_sources[0x5e]	3386	1			T5	16		T6	1		T7	22
valid_sources[0x5f]	4504	1			T4	2		T5	14		T6	7
valid_sources[0x60]	2893	1			T4	1		T5	10		T6	3
valid_sources[0x61]	4559	1			T4	1		T5	11		T8	12
valid_sources[0x62]	3955	1			T5	12		T8	14		T9	13
valid_sources[0x63]	3684	1			T5	14		T7	21		T8	12
valid_sources[0x64]	3318	1			T4	1		T5	6		T8	8
valid_sources[0x65]	3109	1			T4	1		T5	10		T8	18
valid_sources[0x66]	3533	1			T4	1		T5	18		T6	2
valid_sources[0x67]	3345	1			T4	1		T5	6		T8	7
valid_sources[0x68]	3446	1			T5	11		T8	5		T9	10
valid_sources[0x69]	3126	1			T4	1		T5	18		T8	15
valid_sources[0x6a]	3529	1			T4	2		T5	9		T6	2
valid_sources[0x6b]	3197	1			T5	11		T8	12		T9	14
valid_sources[0x6c]	3217	1			T4	1		T5	14		T8	11
valid_sources[0x6d]	3348	1			T4	1		T5	9		T8	4
valid_sources[0x6e]	3850	1			T1	2		T5	14		T8	17
valid_sources[0x6f]	3903	1			T5	12		T7	3		T8	11
valid_sources[0x70]	3295	1			T4	2		T5	12		T8	10
valid_sources[0x71]	3902	1			T5	10		T6	9		T8	8
valid_sources[0x72]	3436	1			T5	10		T6	2		T8	7
valid_sources[0x73]	3304	1			T4	2		T5	17		T7	7
valid_sources[0x74]	3387	1			T5	22		T8	11		T9	8
valid_sources[0x75]	3438	1			T5	14		T8	16		T9	12
valid_sources[0x76]	3708	1			T4	4		T5	15		T8	7
valid_sources[0x77]	3833	1			T1	4		T4	1		T5	20
valid_sources[0x78]	3142	1			T4	2		T5	7		T6	5
valid_sources[0x79]	3248	1			T4	1		T5	10		T8	4
valid_sources[0x7a]	6921	1			T4	2		T5	10		T8	18
valid_sources[0x7b]	3253	1			T4	1		T5	7		T8	10
valid_sources[0x7c]	3218	1			T5	11		T8	17		T9	15
valid_sources[0x7d]	3572	1			T4	1		T5	7		T6	1
valid_sources[0x7e]	2879	1			T5	15		T8	16		T9	10
valid_sources[0x7f]	3077	1			T4	1		T5	13		T8	15
valid_sources[0x80]	4116	1			T4	2		T5	9		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

235959

1

T1

5

T2

4

T3

697

values[0x0]

all_enables

biggest_size

77035

1

T1

2

T2

2

T3

280

values[0x1]

all_enables

biggest_size

41572

1

T1

1

T2

1

T3

143