Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T8
1	0	Covered	T5,T8,T24

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52141791	8142	0	0
CascadeEffAonToRstPorAboveRise_A	52141791	8142	0	0
CascadeEffAonToRstPorIoAboveFall_A	50054282	8142	0	0
CascadeEffAonToRstPorIoAboveRise_A	50054282	8142	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25028103	8142	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25028103	8142	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12513601	8142	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12513601	8142	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25028159	8142	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25028159	8142	0	0
CascadeLcToLcAboveFall_A	52141791	20764	0	0
CascadeLcToLcAboveRise_A	52141791	20764	0	0
CascadeLcToLcAonAboveFall_A	1579901	20764	0	0
CascadeLcToLcAonAboveRise_A	1579901	20764	0	0
CascadeLcToLcShadowedAboveFall_A	52141791	20764	0	0
CascadeLcToLcShadowedAboveRise_A	52141791	20764	0	0
CascadePorToAonAboveFall_A	1579901	6402	0	0
CascadeSysToSysAboveFall_A	52141791	20764	0	0
CascadeSysToSysAboveRise_A	52141791	20764	0	0
ScanRstToAonRise_A	1579901	186	0	0
StablePorToAonRise_A	1579901	8142	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11085433	20764	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11085433	20764	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11085433	20764	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11085433	20764	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12513601	20764	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12513601	20764	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11085433	20764	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11085433	20764	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11085433	20764	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11085433	20764	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	8142	0	0
T1	6812	1	0	0
T2	5927	1	0	0
T3	187892	27	0	0
T4	15683	2	0	0
T5	179442	20	0	0
T6	12133	2	0	0
T7	11051	1	0	0
T8	89525	20	0	0
T9	234969	27	0	0
T10	14772	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	8142	0	0
T1	6812	1	0	0
T2	5927	1	0	0
T3	187892	27	0	0
T4	15683	2	0	0
T5	179442	20	0	0
T6	12133	2	0	0
T7	11051	1	0	0
T8	89525	20	0	0
T9	234969	27	0	0
T10	14772	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50054282	8142	0	0
T1	6538	1	0	0
T2	5690	1	0	0
T3	180405	27	0	0
T4	15054	2	0	0
T5	172270	20	0	0
T6	11647	2	0	0
T7	10608	1	0	0
T8	85889	20	0	0
T9	225580	27	0	0
T10	14173	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50054282	8142	0	0
T1	6538	1	0	0
T2	5690	1	0	0
T3	180405	27	0	0
T4	15054	2	0	0
T5	172270	20	0	0
T6	11647	2	0	0
T7	10608	1	0	0
T8	85889	20	0	0
T9	225580	27	0	0
T10	14173	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028103	8142	0	0
T1	3269	1	0	0
T2	2844	1	0	0
T3	90202	27	0	0
T4	7523	2	0	0
T5	86123	20	0	0
T6	5824	2	0	0
T7	5304	1	0	0
T8	42950	20	0	0
T9	112802	27	0	0
T10	7087	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028103	8142	0	0
T1	3269	1	0	0
T2	2844	1	0	0
T3	90202	27	0	0
T4	7523	2	0	0
T5	86123	20	0	0
T6	5824	2	0	0
T7	5304	1	0	0
T8	42950	20	0	0
T9	112802	27	0	0
T10	7087	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	8142	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	27	0	0
T4	3763	2	0	0
T5	43063	20	0	0
T6	2910	2	0	0
T7	2652	1	0	0
T8	21482	20	0	0
T9	56399	27	0	0
T10	3542	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	8142	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	27	0	0
T4	3763	2	0	0
T5	43063	20	0	0
T6	2910	2	0	0
T7	2652	1	0	0
T8	21482	20	0	0
T9	56399	27	0	0
T10	3542	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028159	8142	0	0
T1	3269	1	0	0
T2	2844	1	0	0
T3	90197	27	0	0
T4	7526	2	0	0
T5	86123	20	0	0
T6	5824	2	0	0
T7	5304	1	0	0
T8	42968	20	0	0
T9	112803	27	0	0
T10	7090	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028159	8142	0	0
T1	3269	1	0	0
T2	2844	1	0	0
T3	90197	27	0	0
T4	7526	2	0	0
T5	86123	20	0	0
T6	5824	2	0	0
T7	5304	1	0	0
T8	42968	20	0	0
T9	112803	27	0	0
T10	7090	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	20764	0	0
T1	6812	2	0	0
T2	5927	2	0	0
T3	187892	102	0	0
T4	15683	6	0	0
T5	179442	53	0	0
T6	12133	6	0	0
T7	11051	11	0	0
T8	89525	52	0	0
T9	234969	102	0	0
T10	14772	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	20764	0	0
T1	6812	2	0	0
T2	5927	2	0	0
T3	187892	102	0	0
T4	15683	6	0	0
T5	179442	53	0	0
T6	12133	6	0	0
T7	11051	11	0	0
T8	89525	52	0	0
T9	234969	102	0	0
T10	14772	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	20764	0	0
T1	203	2	0	0
T2	177	2	0	0
T3	5652	102	0	0
T4	469	6	0	0
T5	5481	53	0	0
T6	362	6	0	0
T7	330	11	0	0
T8	2749	52	0	0
T9	7064	102	0	0
T10	442	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	20764	0	0
T1	203	2	0	0
T2	177	2	0	0
T3	5652	102	0	0
T4	469	6	0	0
T5	5481	53	0	0
T6	362	6	0	0
T7	330	11	0	0
T8	2749	52	0	0
T9	7064	102	0	0
T10	442	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	20764	0	0
T1	6812	2	0	0
T2	5927	2	0	0
T3	187892	102	0	0
T4	15683	6	0	0
T5	179442	53	0	0
T6	12133	6	0	0
T7	11051	11	0	0
T8	89525	52	0	0
T9	234969	102	0	0
T10	14772	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	20764	0	0
T1	6812	2	0	0
T2	5927	2	0	0
T3	187892	102	0	0
T4	15683	6	0	0
T5	179442	53	0	0
T6	12133	6	0	0
T7	11051	11	0	0
T8	89525	52	0	0
T9	234969	102	0	0
T10	14772	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	6402	0	0
T1	203	1	0	0
T2	177	1	0	0
T3	5652	27	0	0
T4	469	1	0	0
T5	5481	12	0	0
T6	362	1	0	0
T7	330	1	0	0
T8	2749	12	0	0
T9	7064	27	0	0
T10	442	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	20764	0	0
T1	6812	2	0	0
T2	5927	2	0	0
T3	187892	102	0	0
T4	15683	6	0	0
T5	179442	53	0	0
T6	12133	6	0	0
T7	11051	11	0	0
T8	89525	52	0	0
T9	234969	102	0	0
T10	14772	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52141791	20764	0	0
T1	6812	2	0	0
T2	5927	2	0	0
T3	187892	102	0	0
T4	15683	6	0	0
T5	179442	53	0	0
T6	12133	6	0	0
T7	11051	11	0	0
T8	89525	52	0	0
T9	234969	102	0	0
T10	14772	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	186	0	0
T13	291	0	0	0
T14	444	0	0	0
T24	4022	1	0	0
T25	463	0	0	0
T26	4933	2	0	0
T27	393	0	0	0
T28	1138	0	0	0
T53	0	1	0	0
T55	0	6	0	0
T63	335	0	0	0
T81	14752	1	0	0
T84	481	0	0	0
T89	0	5	0	0
T101	0	1	0	0
T103	0	1	0	0
T111	0	1	0	0
T132	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	8142	0	0
T1	203	1	0	0
T2	177	1	0	0
T3	5652	27	0	0
T4	469	2	0	0
T5	5481	20	0	0
T6	362	2	0	0
T7	330	1	0	0
T8	2749	20	0	0
T9	7064	27	0	0
T10	442	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	20764	0	0
T1	1633	2	0	0
T2	1422	2	0	0
T3	45096	102	0	0
T4	3763	6	0	0
T5	43063	53	0	0
T6	2910	6	0	0
T7	2652	11	0	0
T8	21482	52	0	0
T9	56399	102	0	0
T10	3542	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	20764	0	0
T1	1633	2	0	0
T2	1422	2	0	0
T3	45096	102	0	0
T4	3763	6	0	0
T5	43063	53	0	0
T6	2910	6	0	0
T7	2652	11	0	0
T8	21482	52	0	0
T9	56399	102	0	0
T10	3542	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11085433	20764	0	0
T1	1469	2	0	0
T2	1353	2	0	0
T3	41986	102	0	0
T4	3472	6	0	0
T5	39037	53	0	0
T6	2769	6	0	0
T7	1999	11	0	0
T8	17018	52	0	0
T9	53308	102	0	0
T10	3348	6	0	0