Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T23,T27
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T28,T81
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T28
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T28,T81
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T27,T28,T81
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T27,T28
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T28,T81
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T81,T83
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12513601	13321	0	0
gen_assertions[0].RstEnOn_A	12513601	904	0	0
gen_assertions[0].RstNOff_A	12513601	13321	0	0
gen_assertions[0].RstNOn_A	12513601	904	0	0
gen_assertions[1].RstEnOff_A	50054282	12049	0	0
gen_assertions[1].RstEnOn_A	50054282	845	0	0
gen_assertions[1].RstNOff_A	50054282	12049	0	0
gen_assertions[1].RstNOn_A	50054282	845	0	0
gen_assertions[2].RstEnOff_A	25028103	12102	0	0
gen_assertions[2].RstEnOn_A	25028103	835	0	0
gen_assertions[2].RstNOff_A	25028103	12102	0	0
gen_assertions[2].RstNOn_A	25028103	835	0	0
gen_assertions[3].RstEnOff_A	25028159	12146	0	0
gen_assertions[3].RstEnOn_A	25028159	870	0	0
gen_assertions[3].RstNOff_A	25028159	12146	0	0
gen_assertions[3].RstNOn_A	25028159	870	0	0
gen_assertions[4].RstEnOff_A	1579901	20471	0	0
gen_assertions[4].RstEnOn_A	1579901	919	0	0
gen_assertions[4].RstNOff_A	1579901	20471	0	0
gen_assertions[4].RstNOn_A	1579901	919	0	0
gen_assertions[5].RstEnOff_A	12513601	13580	0	0
gen_assertions[5].RstEnOn_A	12513601	989	0	0
gen_assertions[5].RstNOff_A	12513601	13580	0	0
gen_assertions[5].RstNOn_A	12513601	989	0	0
gen_assertions[6].RstEnOff_A	12513601	13604	0	0
gen_assertions[6].RstEnOn_A	12513601	1018	0	0
gen_assertions[6].RstNOff_A	12513601	13604	0	0
gen_assertions[6].RstNOn_A	12513601	1018	0	0
gen_assertions[7].RstEnOff_A	12513601	13662	0	0
gen_assertions[7].RstEnOn_A	12513601	1077	0	0
gen_assertions[7].RstNOff_A	12513601	13662	0	0
gen_assertions[7].RstNOn_A	12513601	1077	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13321	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	4	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	904	0	0
T7	2652	2	0	0
T8	21482	0	0	0
T9	56399	0	0	0
T10	3542	0	0	0
T11	2079	0	0	0
T12	3230	0	0	0
T21	4935	0	0	0
T22	5422	0	0	0
T23	4753	2	0	0
T24	31835	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	10	0	0
T81	0	18	0	0
T83	0	1	0	0
T84	0	8	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13321	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	4	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	904	0	0
T7	2652	2	0	0
T8	21482	0	0	0
T9	56399	0	0	0
T10	3542	0	0	0
T11	2079	0	0	0
T12	3230	0	0	0
T21	4935	0	0	0
T22	5422	0	0	0
T23	4753	2	0	0
T24	31835	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	10	0	0
T81	0	18	0	0
T83	0	1	0	0
T84	0	8	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50054282	12049	0	0
T2	5690	1	0	0
T3	180405	61	0	0
T4	15054	3	0	0
T5	172270	31	0	0
T6	11647	4	0	0
T7	10608	10	0	0
T8	85889	30	0	0
T9	225580	64	0	0
T10	14173	4	0	0
T11	8322	0	0	0
T21	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50054282	845	0	0
T7	10608	2	0	0
T8	85889	0	0	0
T9	225580	0	0	0
T10	14173	0	0	0
T11	8322	0	0	0
T12	12920	0	0	0
T21	19743	0	0	0
T22	21697	0	0	0
T23	19015	0	0	0
T24	127318	0	0	0
T28	0	4	0	0
T55	0	8	0	0
T57	0	3	0	0
T58	0	7	0	0
T81	0	16	0	0
T83	0	2	0	0
T84	0	5	0	0
T85	0	12	0	0
T86	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50054282	12049	0	0
T2	5690	1	0	0
T3	180405	61	0	0
T4	15054	3	0	0
T5	172270	31	0	0
T6	11647	4	0	0
T7	10608	10	0	0
T8	85889	30	0	0
T9	225580	64	0	0
T10	14173	4	0	0
T11	8322	0	0	0
T21	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50054282	845	0	0
T7	10608	2	0	0
T8	85889	0	0	0
T9	225580	0	0	0
T10	14173	0	0	0
T11	8322	0	0	0
T12	12920	0	0	0
T21	19743	0	0	0
T22	21697	0	0	0
T23	19015	0	0	0
T24	127318	0	0	0
T28	0	4	0	0
T55	0	8	0	0
T57	0	3	0	0
T58	0	7	0	0
T81	0	16	0	0
T83	0	2	0	0
T84	0	5	0	0
T85	0	12	0	0
T86	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028103	12102	0	0
T2	2844	1	0	0
T3	90202	61	0	0
T4	7523	3	0	0
T5	86123	31	0	0
T6	5824	4	0	0
T7	5304	10	0	0
T8	42950	30	0	0
T9	112802	64	0	0
T10	7087	4	0	0
T11	4161	0	0	0
T21	0	5	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028103	835	0	0
T12	6460	0	0	0
T21	9872	1	0	0
T22	10847	1	0	0
T23	9508	0	0	0
T24	63662	0	0	0
T25	7424	0	0	0
T26	77994	0	0	0
T27	6319	0	0	0
T28	18225	6	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	9	0	0
T57	0	3	0	0
T81	231937	14	0	0
T83	0	2	0	0
T87	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028103	12102	0	0
T2	2844	1	0	0
T3	90202	61	0	0
T4	7523	3	0	0
T5	86123	31	0	0
T6	5824	4	0	0
T7	5304	10	0	0
T8	42950	30	0	0
T9	112802	64	0	0
T10	7087	4	0	0
T11	4161	0	0	0
T21	0	5	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028103	835	0	0
T12	6460	0	0	0
T21	9872	1	0	0
T22	10847	1	0	0
T23	9508	0	0	0
T24	63662	0	0	0
T25	7424	0	0	0
T26	77994	0	0	0
T27	6319	0	0	0
T28	18225	6	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	9	0	0
T57	0	3	0	0
T81	231937	14	0	0
T83	0	2	0	0
T87	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028159	12146	0	0
T2	2844	1	0	0
T3	90197	61	0	0
T4	7526	3	0	0
T5	86123	31	0	0
T6	5824	4	0	0
T7	5304	10	0	0
T8	42968	30	0	0
T9	112803	64	0	0
T10	7090	4	0	0
T11	4160	0	0	0
T21	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028159	870	0	0
T12	6460	0	0	0
T21	9873	1	0	0
T22	10848	0	0	0
T23	9507	0	0	0
T24	63662	0	0	0
T25	7426	0	0	0
T26	78000	0	0	0
T27	6317	0	0	0
T28	18224	6	0	0
T55	0	9	0	0
T57	0	4	0	0
T58	0	7	0	0
T81	231934	18	0	0
T83	0	4	0	0
T85	0	7	0	0
T88	0	5	0	0
T89	0	3	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028159	12146	0	0
T2	2844	1	0	0
T3	90197	61	0	0
T4	7526	3	0	0
T5	86123	31	0	0
T6	5824	4	0	0
T7	5304	10	0	0
T8	42968	30	0	0
T9	112803	64	0	0
T10	7090	4	0	0
T11	4160	0	0	0
T21	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25028159	870	0	0
T12	6460	0	0	0
T21	9873	1	0	0
T22	10848	0	0	0
T23	9507	0	0	0
T24	63662	0	0	0
T25	7426	0	0	0
T26	78000	0	0	0
T27	6317	0	0	0
T28	18224	6	0	0
T55	0	9	0	0
T57	0	4	0	0
T58	0	7	0	0
T81	231934	18	0	0
T83	0	4	0	0
T85	0	7	0	0
T88	0	5	0	0
T89	0	3	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	20471	0	0
T1	203	2	0	0
T2	177	2	0	0
T3	5652	95	0	0
T4	469	5	0	0
T5	5481	52	0	0
T6	362	6	0	0
T7	330	11	0	0
T8	2749	52	0	0
T9	7064	97	0	0
T10	442	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	919	0	0
T13	291	0	0	0
T14	444	0	0	0
T27	393	1	0	0
T28	1138	7	0	0
T29	7078	0	0	0
T49	728	1	0	0
T55	0	9	0	0
T57	0	7	0	0
T58	0	10	0	0
T63	335	0	0	0
T81	14752	17	0	0
T83	942	3	0	0
T84	481	0	0	0
T85	0	8	0	0
T90	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	20471	0	0
T1	203	2	0	0
T2	177	2	0	0
T3	5652	95	0	0
T4	469	5	0	0
T5	5481	52	0	0
T6	362	6	0	0
T7	330	11	0	0
T8	2749	52	0	0
T9	7064	97	0	0
T10	442	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1579901	919	0	0
T13	291	0	0	0
T14	444	0	0	0
T27	393	1	0	0
T28	1138	7	0	0
T29	7078	0	0	0
T49	728	1	0	0
T55	0	9	0	0
T57	0	7	0	0
T58	0	10	0	0
T63	335	0	0	0
T81	14752	17	0	0
T83	942	3	0	0
T84	481	0	0	0
T85	0	8	0	0
T90	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13580	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	4	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	989	0	0
T12	3230	0	0	0
T21	4935	1	0	0
T22	5422	0	0	0
T23	4753	0	0	0
T24	31835	0	0	0
T25	3711	0	0	0
T26	38998	0	0	0
T27	3156	1	0	0
T28	9111	8	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	9	0	0
T57	0	7	0	0
T63	0	1	0	0
T81	115964	18	0	0
T83	0	3	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13580	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	4	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	989	0	0
T12	3230	0	0	0
T21	4935	1	0	0
T22	5422	0	0	0
T23	4753	0	0	0
T24	31835	0	0	0
T25	3711	0	0	0
T26	38998	0	0	0
T27	3156	1	0	0
T28	9111	8	0	0
T49	0	1	0	0
T54	0	1	0	0
T55	0	9	0	0
T57	0	7	0	0
T63	0	1	0	0
T81	115964	18	0	0
T83	0	3	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13604	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	5	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	1018	0	0
T6	2910	1	0	0
T7	2652	0	0	0
T8	21482	0	0	0
T9	56399	0	0	0
T10	3542	0	0	0
T11	2079	0	0	0
T12	3230	0	0	0
T21	4935	0	0	0
T22	5422	0	0	0
T23	4753	0	0	0
T28	0	8	0	0
T49	0	1	0	0
T55	0	12	0	0
T57	0	8	0	0
T58	0	12	0	0
T81	0	16	0	0
T83	0	2	0	0
T85	0	9	0	0
T90	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13604	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	5	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	1018	0	0
T6	2910	1	0	0
T7	2652	0	0	0
T8	21482	0	0	0
T9	56399	0	0	0
T10	3542	0	0	0
T11	2079	0	0	0
T12	3230	0	0	0
T21	4935	0	0	0
T22	5422	0	0	0
T23	4753	0	0	0
T28	0	8	0	0
T49	0	1	0	0
T55	0	12	0	0
T57	0	8	0	0
T58	0	12	0	0
T81	0	16	0	0
T83	0	2	0	0
T85	0	9	0	0
T90	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13662	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	4	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	1077	0	0
T13	2341	0	0	0
T14	3556	0	0	0
T15	3275	0	0	0
T28	9111	9	0	0
T29	56505	0	0	0
T49	5833	1	0	0
T55	0	10	0	0
T57	0	9	0	0
T58	0	12	0	0
T63	2682	0	0	0
T81	115964	15	0	0
T83	7537	3	0	0
T84	3854	0	0	0
T85	0	9	0	0
T88	0	9	0	0
T90	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	13662	0	0
T1	1633	1	0	0
T2	1422	1	0	0
T3	45096	75	0	0
T4	3763	4	0	0
T5	43063	33	0	0
T6	2910	4	0	0
T7	2652	10	0	0
T8	21482	32	0	0
T9	56399	75	0	0
T10	3542	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12513601	1077	0	0
T13	2341	0	0	0
T14	3556	0	0	0
T15	3275	0	0	0
T28	9111	9	0	0
T29	56505	0	0	0
T49	5833	1	0	0
T55	0	10	0	0
T57	0	9	0	0
T58	0	12	0	0
T63	2682	0	0	0
T81	115964	15	0	0
T83	7537	3	0	0
T84	3854	0	0	0
T85	0	9	0	0
T88	0	9	0	0
T90	0	1	0	0