Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11875366	8132	0	0
alert_regwen_rd_A	11875366	5078	0	0
cpu_regwen_rd_A	11875366	5021	0	0
sw_rst_ctrl_n_0_rd_A	11875366	10829	0	0
sw_rst_ctrl_n_1_rd_A	11875366	10632	0	0
sw_rst_ctrl_n_2_rd_A	11875366	10996	0	0
sw_rst_ctrl_n_3_rd_A	11875366	10805	0	0
sw_rst_ctrl_n_4_rd_A	11875366	10875	0	0
sw_rst_ctrl_n_5_rd_A	11875366	10587	0	0
sw_rst_ctrl_n_6_rd_A	11875366	10762	0	0
sw_rst_ctrl_n_7_rd_A	11875366	10962	0	0
sw_rst_regwen_0_rd_A	11875366	5802	0	0
sw_rst_regwen_1_rd_A	11875366	5669	0	0
sw_rst_regwen_2_rd_A	11875366	5744	0	0
sw_rst_regwen_3_rd_A	11875366	5976	0	0
sw_rst_regwen_4_rd_A	11875366	5904	0	0
sw_rst_regwen_5_rd_A	11875366	6031	0	0
sw_rst_regwen_6_rd_A	11875366	5885	0	0
sw_rst_regwen_7_rd_A	11875366	5865	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	8132	0	0
T59	21354	1	0	0
T62	4075	65	0	0
T64	11528	433	0	0
T65	4978	25	0	0
T66	21021	1	0	0
T67	18165	3	0	0
T93	11784	1	0	0
T95	10218	1	0	0
T96	3485	353	0	0
T98	9066	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5078	0	0
T5	39037	71	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	0	0	0
T26	0	50	0	0
T55	0	199	0	0
T101	0	19	0	0
T106	0	338	0	0
T107	0	95	0	0
T110	0	219	0	0
T111	0	35	0	0
T130	0	89	0	0
T131	0	226	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5021	0	0
T5	39037	72	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	0	0	0
T26	0	47	0	0
T55	0	145	0	0
T101	0	37	0	0
T106	0	306	0	0
T107	0	99	0	0
T110	0	242	0	0
T111	0	40	0	0
T130	0	57	0	0
T131	0	217	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10829	0	0
T5	39037	81	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	10	0	0
T23	0	33	0	0
T26	0	44	0	0
T28	0	76	0	0
T49	0	9	0	0
T55	0	271	0	0
T57	0	138	0	0
T58	0	169	0	0
T101	0	22	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10632	0	0
T5	39037	62	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	4	0	0
T23	0	51	0	0
T26	0	49	0	0
T28	0	115	0	0
T49	0	3	0	0
T55	0	215	0	0
T57	0	143	0	0
T58	0	192	0	0
T101	0	49	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10996	0	0
T5	39037	83	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	15	0	0
T23	0	33	0	0
T26	0	49	0	0
T28	0	94	0	0
T49	0	12	0	0
T55	0	265	0	0
T57	0	120	0	0
T58	0	216	0	0
T101	0	43	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10805	0	0
T5	39037	66	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	7	0	0
T23	0	34	0	0
T26	0	64	0	0
T28	0	106	0	0
T49	0	9	0	0
T55	0	236	0	0
T57	0	124	0	0
T58	0	192	0	0
T101	0	47	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10875	0	0
T5	39037	59	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	2	0	0
T23	0	31	0	0
T26	0	48	0	0
T28	0	58	0	0
T49	0	6	0	0
T55	0	273	0	0
T57	0	132	0	0
T58	0	186	0	0
T101	0	41	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10587	0	0
T5	39037	62	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	7	0	0
T23	0	34	0	0
T26	0	49	0	0
T28	0	105	0	0
T49	0	10	0	0
T55	0	195	0	0
T57	0	153	0	0
T58	0	194	0	0
T101	0	42	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10762	0	0
T5	39037	85	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	10	0	0
T23	0	45	0	0
T26	0	40	0	0
T28	0	56	0	0
T49	0	20	0	0
T55	0	215	0	0
T57	0	144	0	0
T58	0	177	0	0
T101	0	33	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	10962	0	0
T5	39037	71	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	14	0	0
T23	0	49	0	0
T26	0	54	0	0
T28	0	89	0	0
T49	0	2	0	0
T55	0	239	0	0
T57	0	160	0	0
T58	0	186	0	0
T101	0	35	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5802	0	0
T5	39037	61	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	11	0	0
T26	0	70	0	0
T28	0	22	0	0
T49	0	5	0	0
T55	0	129	0	0
T57	0	32	0	0
T58	0	29	0	0
T101	0	48	0	0
T111	0	40	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5669	0	0
T5	39037	66	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	8	0	0
T26	0	54	0	0
T28	0	17	0	0
T49	0	6	0	0
T55	0	168	0	0
T57	0	38	0	0
T58	0	30	0	0
T101	0	43	0	0
T111	0	49	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5744	0	0
T5	39037	75	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	0	0	0
T26	0	39	0	0
T28	0	20	0	0
T49	0	4	0	0
T55	0	135	0	0
T57	0	38	0	0
T58	0	25	0	0
T88	0	51	0	0
T101	0	35	0	0
T111	0	22	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5976	0	0
T5	39037	72	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	5	0	0
T26	0	59	0	0
T28	0	14	0	0
T49	0	3	0	0
T55	0	162	0	0
T57	0	38	0	0
T58	0	36	0	0
T101	0	24	0	0
T111	0	38	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5904	0	0
T5	39037	61	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	7	0	0
T26	0	47	0	0
T28	0	20	0	0
T49	0	8	0	0
T55	0	139	0	0
T57	0	29	0	0
T58	0	36	0	0
T101	0	57	0	0
T111	0	42	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	6031	0	0
T5	39037	68	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	0	0	0
T26	0	55	0	0
T28	0	21	0	0
T49	0	7	0	0
T55	0	179	0	0
T57	0	41	0	0
T58	0	20	0	0
T88	0	29	0	0
T101	0	39	0	0
T111	0	49	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5885	0	0
T5	39037	64	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	1	0	0
T26	0	55	0	0
T28	0	19	0	0
T49	0	4	0	0
T55	0	155	0	0
T57	0	28	0	0
T58	0	38	0	0
T101	0	60	0	0
T111	0	34	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11875366	5865	0	0
T5	39037	76	0	0
T6	2769	0	0	0
T7	1999	0	0	0
T8	17018	0	0	0
T9	53308	0	0	0
T10	3348	0	0	0
T11	2013	0	0	0
T12	3139	0	0	0
T21	4647	0	0	0
T22	5135	7	0	0
T26	0	58	0	0
T28	0	23	0	0
T49	0	5	0	0
T55	0	192	0	0
T57	0	32	0	0
T58	0	34	0	0
T101	0	42	0	0
T111	0	35	0	0