Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sw_rst_ctrl_n[0]	100.00	1	100	1	64	64
sw_rst_ctrl_n[1]	100.00	1	100	1	64	64
sw_rst_ctrl_n[2]	100.00	1	100	1	64	64
sw_rst_ctrl_n[3]	100.00	1	100	1	64	64
sw_rst_ctrl_n[4]	100.00	1	100	1	64	64
sw_rst_ctrl_n[5]	100.00	1	100	1	64	64
sw_rst_ctrl_n[6]	100.00	1	100	1	64	64
sw_rst_ctrl_n[7]	100.00	1	100	1	64	64

---

Group Instance : sw_rst_ctrl_n[0]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[0]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[0]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[1]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[1]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[1]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[2]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[2]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[2]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[3]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[3]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[3]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[4]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[4]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[4]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[5]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[5]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[5]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[6]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[6]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[6]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[7]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[7]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[7]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T20

32

T65

32

T44

32

auto[1]

4880

1

T6

38

T10

3

T20

26

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T20

32

T65

32

T44

32

auto[1]

4880

1

T6

38

T10

3

T20

26

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1885

1

T6

12

T10

1

T20

19

auto[1]

4595

1

T6

26

T10

2

T20

39

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1885

1

T6

12

T10

1

T20

19

auto[1]

4595

1

T6

26

T10

2

T20

39

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

400

1

T20

8

T65

8

T44

8

auto[0]

auto[1]

1200

1

T20

24

T65

24

T44

24

auto[1]

auto[0]

1485

1

T6

12

T10

1

T20

11

auto[1]

auto[1]

3395

1

T6

26

T10

2

T20

15

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1487

1

T20

28

T63

3

T65

28

auto[1]

4765

1

T6

27

T10

3

T20

30

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1487

1

T20

28

T63

3

T65

28

auto[1]

4765

1

T6

27

T10

3

T20

30

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1749

1

T6

5

T20

19

T60

1

auto[1]

4503

1

T6

22

T10

3

T20

39

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1749

1

T6

5

T20

19

T60

1

auto[1]

4503

1

T6

22

T10

3

T20

39

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

396

1

T20

7

T63

2

T65

7

auto[0]

auto[1]

1091

1

T20

21

T63

1

T65

21

auto[1]

auto[0]

1353

1

T6

5

T20

12

T60

1

auto[1]

auto[1]

3412

1

T6

22

T10

3

T20

18

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T20

24

T62

3

T63

3

auto[1]

4876

1

T6

20

T10

3

T20

34

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T20

24

T62

3

T63

3

auto[1]

4876

1

T6

20

T10

3

T20

34

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1733

1

T10

1

T20

17

T62

2

auto[1]

4415

1

T6

20

T10

2

T20

41

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1733

1

T10

1

T20

17

T62

2

auto[1]

4415

1

T6

20

T10

2

T20

41

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

333

1

T20

6

T62

2

T63

2

auto[0]

auto[1]

939

1

T20

18

T62

1

T63

1

auto[1]

auto[0]

1400

1

T10

1

T20

11

T53

18

auto[1]

auto[1]

3476

1

T6

20

T10

2

T20

23

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T20

20

T62

3

T65

20

auto[1]

5062

1

T6

19

T10

3

T20

38

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T20

20

T62

3

T65

20

auto[1]

5062

1

T6

19

T10

3

T20

38

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1749

1

T10

1

T20

18

T60

1

auto[1]

4385

1

T6

19

T10

2

T20

40

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1749

1

T10

1

T20

18

T60

1

auto[1]

4385

1

T6

19

T10

2

T20

40

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

286

1

T20

5

T62

1

T65

5

auto[0]

auto[1]

786

1

T20

15

T62

2

T65

15

auto[1]

auto[0]

1463

1

T10

1

T20

13

T60

1

auto[1]

auto[1]

3599

1

T6

19

T10

2

T20

25

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875

1

T10

3

T20

16

T62

3

auto[1]

5259

1

T6

19

T20

42

T22

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875

1

T10

3

T20

16

T62

3

auto[1]

5259

1

T6

19

T20

42

T22

1

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1755

1

T10

2

T20

13

T62

1

auto[1]

4379

1

T6

19

T10

1

T20

45

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1755

1

T10

2

T20

13

T62

1

auto[1]

4379

1

T6

19

T10

1

T20

45

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

236

1

T10

2

T20

4

T62

1

auto[0]

auto[1]

639

1

T10

1

T20

12

T62

2

auto[1]

auto[0]

1519

1

T20

9

T53

25

T54

3

auto[1]

auto[1]

3740

1

T6

19

T20

33

T22

1

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T20

12

T60

3

T62

3

auto[1]

5459

1

T6

19

T10

3

T20

46

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T20

12

T60

3

T62

3

auto[1]

5459

1

T6

19

T10

3

T20

46

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1726

1

T10

1

T20

16

T60

1

auto[1]

4408

1

T6

19

T10

2

T20

42

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1726

1

T10

1

T20

16

T60

1

auto[1]

4408

1

T6

19

T10

2

T20

42

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

189

1

T20

3

T60

1

T62

1

auto[0]

auto[1]

486

1

T20

9

T60

2

T62

2

auto[1]

auto[0]

1537

1

T10

1

T20

13

T53

19

auto[1]

auto[1]

3922

1

T6

19

T10

2

T20

33

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

469

1

T20

8

T60

3

T65

8

auto[1]

5665

1

T6

19

T10

3

T20

50

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

469

1

T20

8

T60

3

T65

8

auto[1]

5665

1

T6

19

T10

3

T20

50

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1727

1

T20

15

T60

1

T62

1

auto[1]

4407

1

T6

19

T10

3

T20

43

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1727

1

T20

15

T60

1

T62

1

auto[1]

4407

1

T6

19

T10

3

T20

43

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

134

1

T20

2

T60

1

T65

2

auto[0]

auto[1]

335

1

T20

6

T60

2

T65

6

auto[1]

auto[0]

1593

1

T20

13

T62

1

T63

1

auto[1]

auto[1]

4072

1

T6

19

T10

3

T20

37

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

257

1

T10

3

T20

4

T63

3

auto[1]

5877

1

T6

19

T20

54

T22

1

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

257

1

T10

3

T20

4

T63

3

auto[1]

5877

1

T6

19

T20

54

T22

1

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690

1

T10

2

T20

19

T60

1

auto[1]

4444

1

T6

19

T10

1

T20

39

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690

1

T10

2

T20

19

T60

1

auto[1]

4444

1

T6

19

T10

1

T20

39

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

77

1

T10

2

T20

1

T63

2

auto[0]

auto[1]

180

1

T10

1

T20

3

T63

1

auto[1]

auto[0]

1613

1

T20

18

T60

1

T53

19

auto[1]

auto[1]

4264

1

T6

19

T20

36

T22

1