Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	598287	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

359995

1

T1

64

T3

214

T4

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	510494	1			T1	99		T3	297		T4	99
values[0x0]	223810	1			T1	59		T3	165		T4	59
values[0x1]	223978	1			T1	54		T3	174		T4	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	502038	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

456244

1

T1

83

T3

280

T4

86

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3368	1			T1	5		T6	1		T7	10
valid_sources[0x01]	3426	1			T1	2		T4	1		T6	5
valid_sources[0x02]	4063	1			T1	1		T4	1		T6	2
valid_sources[0x03]	4293	1			T1	1		T3	3		T6	3
valid_sources[0x04]	3269	1			T1	2		T5	1		T6	2
valid_sources[0x05]	3913	1			T3	9		T4	1		T6	4
valid_sources[0x06]	3688	1			T3	6		T6	5		T7	5
valid_sources[0x07]	3702	1			T6	3		T7	5		T9	13
valid_sources[0x08]	3600	1			T4	4		T6	1		T7	17
valid_sources[0x09]	4187	1			T3	20		T6	3		T7	10
valid_sources[0x0a]	3370	1			T4	1		T6	4		T7	7
valid_sources[0x0b]	3797	1			T1	1		T4	3		T6	3
valid_sources[0x0c]	3774	1			T6	1		T7	15		T9	11
valid_sources[0x0d]	3458	1			T4	1		T7	9		T9	19
valid_sources[0x0e]	3980	1			T6	2		T7	8		T9	20
valid_sources[0x0f]	3870	1			T1	1		T6	2		T7	11
valid_sources[0x10]	3164	1			T1	3		T4	1		T6	4
valid_sources[0x11]	3161	1			T1	1		T6	4		T7	10
valid_sources[0x12]	3567	1			T1	1		T4	1		T6	1
valid_sources[0x13]	3115	1			T1	2		T6	3		T7	13
valid_sources[0x14]	3413	1			T4	2		T6	4		T7	9
valid_sources[0x15]	3903	1			T3	9		T6	1		T7	11
valid_sources[0x16]	3309	1			T4	1		T6	1		T7	12
valid_sources[0x17]	3676	1			T7	13		T9	20		T20	4
valid_sources[0x18]	3588	1			T1	2		T6	3		T7	12
valid_sources[0x19]	6219	1			T1	2		T4	1		T6	2
valid_sources[0x1a]	3995	1			T6	1		T7	9		T9	10
valid_sources[0x1b]	4050	1			T4	1		T6	1		T7	6
valid_sources[0x1c]	3396	1			T4	2		T7	13		T9	8
valid_sources[0x1d]	3069	1			T1	1		T4	1		T6	1
valid_sources[0x1e]	3918	1			T4	2		T7	16		T9	12
valid_sources[0x1f]	3726	1			T1	1		T6	1		T7	10
valid_sources[0x20]	3265	1			T3	2		T6	2		T7	14
valid_sources[0x21]	3612	1			T1	1		T6	1		T7	9
valid_sources[0x22]	3748	1			T3	8		T7	12		T9	12
valid_sources[0x23]	4787	1			T3	4		T4	3		T6	2
valid_sources[0x24]	3853	1			T1	3		T4	1		T6	1
valid_sources[0x25]	4174	1			T1	2		T4	3		T6	3
valid_sources[0x26]	3423	1			T1	2		T3	11		T6	1
valid_sources[0x27]	3889	1			T7	8		T9	12		T20	8
valid_sources[0x28]	3566	1			T1	1		T7	10		T9	12
valid_sources[0x29]	3399	1			T1	1		T4	1		T6	1
valid_sources[0x2a]	3731	1			T4	1		T6	3		T7	10
valid_sources[0x2b]	3703	1			T1	3		T3	3		T6	1
valid_sources[0x2c]	4000	1			T1	1		T4	2		T6	1
valid_sources[0x2d]	3000	1			T1	1		T3	6		T6	2
valid_sources[0x2e]	3493	1			T4	2		T6	2		T7	12
valid_sources[0x2f]	4146	1			T3	21		T6	1		T7	8
valid_sources[0x30]	3615	1			T4	2		T7	6		T9	5
valid_sources[0x31]	3487	1			T1	1		T6	2		T7	8
valid_sources[0x32]	3133	1			T1	1		T4	2		T6	1
valid_sources[0x33]	3918	1			T1	1		T3	3		T4	1
valid_sources[0x34]	3240	1			T1	2		T7	4		T9	18
valid_sources[0x35]	2895	1			T1	1		T6	1		T7	4
valid_sources[0x36]	3371	1			T3	3		T6	2		T7	13
valid_sources[0x37]	2992	1			T1	1		T3	8		T4	2
valid_sources[0x38]	3268	1			T1	1		T6	1		T7	14
valid_sources[0x39]	3829	1			T1	1		T6	5		T7	7
valid_sources[0x3a]	3664	1			T4	1		T6	1		T7	10
valid_sources[0x3b]	4080	1			T3	8		T7	7		T9	17
valid_sources[0x3c]	3577	1			T4	3		T6	2		T7	12
valid_sources[0x3d]	3232	1			T1	3		T3	17		T4	2
valid_sources[0x3e]	3699	1			T1	1		T4	1		T6	1
valid_sources[0x3f]	3644	1			T3	10		T4	4		T6	2
valid_sources[0x40]	4209	1			T1	1		T4	1		T6	2
valid_sources[0x41]	3810	1			T4	1		T6	1		T7	9
valid_sources[0x42]	3400	1			T1	1		T3	2		T4	3
valid_sources[0x43]	3253	1			T6	1		T7	10		T9	17
valid_sources[0x44]	5034	1			T1	2		T4	2		T6	2
valid_sources[0x45]	3122	1			T1	1		T4	1		T7	12
valid_sources[0x46]	3248	1			T1	1		T6	1		T7	14
valid_sources[0x47]	3739	1			T1	2		T4	2		T6	2
valid_sources[0x48]	3854	1			T1	2		T6	1		T7	12
valid_sources[0x49]	3217	1			T1	2		T6	2		T7	5
valid_sources[0x4a]	3486	1			T3	25		T6	1		T7	9
valid_sources[0x4b]	4505	1			T3	7		T7	11		T9	6
valid_sources[0x4c]	3837	1			T1	2		T4	3		T6	2
valid_sources[0x4d]	3583	1			T1	2		T4	1		T6	2
valid_sources[0x4e]	4597	1			T1	1		T4	2		T7	13
valid_sources[0x4f]	3112	1			T1	2		T7	12		T9	10
valid_sources[0x50]	3440	1			T1	1		T4	1		T6	1
valid_sources[0x51]	3629	1			T1	1		T4	2		T6	2
valid_sources[0x52]	3455	1			T1	2		T7	10		T9	12
valid_sources[0x53]	3488	1			T3	8		T4	1		T6	2
valid_sources[0x54]	3224	1			T6	1		T7	11		T9	13
valid_sources[0x55]	3947	1			T1	1		T3	21		T4	2
valid_sources[0x56]	2949	1			T1	1		T6	2		T7	10
valid_sources[0x57]	6473	1			T1	1		T4	1		T6	1
valid_sources[0x58]	3932	1			T6	1		T7	11		T9	19
valid_sources[0x59]	3220	1			T3	11		T6	2		T7	3
valid_sources[0x5a]	3156	1			T4	2		T7	8		T9	14
valid_sources[0x5b]	3540	1			T4	1		T7	9		T9	10
valid_sources[0x5c]	3605	1			T1	1		T7	10		T9	12
valid_sources[0x5d]	3855	1			T1	1		T6	2		T7	5
valid_sources[0x5e]	3805	1			T6	1		T7	12		T9	14
valid_sources[0x5f]	3326	1			T1	2		T4	2		T6	1
valid_sources[0x60]	3405	1			T1	1		T3	7		T4	1
valid_sources[0x61]	3934	1			T1	1		T4	3		T6	1
valid_sources[0x62]	3884	1			T1	1		T3	2		T6	2
valid_sources[0x63]	3329	1			T1	2		T7	7		T9	11
valid_sources[0x64]	3627	1			T1	1		T4	2		T7	10
valid_sources[0x65]	3308	1			T1	1		T6	3		T7	11
valid_sources[0x66]	4240	1			T4	5		T6	3		T7	5
valid_sources[0x67]	3612	1			T1	4		T6	2		T7	15
valid_sources[0x68]	3175	1			T1	1		T7	13		T9	14
valid_sources[0x69]	4222	1			T1	1		T3	12		T6	1
valid_sources[0x6a]	3717	1			T1	1		T7	11		T9	15
valid_sources[0x6b]	3746	1			T1	1		T6	2		T7	6
valid_sources[0x6c]	3575	1			T4	1		T7	9		T9	14
valid_sources[0x6d]	4711	1			T6	1		T7	10		T9	15
valid_sources[0x6e]	3841	1			T6	2		T7	14		T9	14
valid_sources[0x6f]	3622	1			T1	2		T4	1		T6	1
valid_sources[0x70]	3663	1			T6	1		T7	9		T9	11
valid_sources[0x71]	3770	1			T1	3		T3	6		T4	1
valid_sources[0x72]	3703	1			T1	2		T3	1		T4	3
valid_sources[0x73]	3369	1			T1	2		T3	10		T4	1
valid_sources[0x74]	3087	1			T6	2		T7	11		T9	18
valid_sources[0x75]	3133	1			T1	1		T6	1		T7	11
valid_sources[0x76]	5715	1			T3	9		T4	4		T6	1
valid_sources[0x77]	3151	1			T1	1		T4	3		T6	1
valid_sources[0x78]	3461	1			T4	1		T6	2		T7	9
valid_sources[0x79]	3104	1			T6	3		T7	8		T9	11
valid_sources[0x7a]	3184	1			T6	2		T7	10		T9	10
valid_sources[0x7b]	4617	1			T1	2		T7	13		T9	11
valid_sources[0x7c]	3703	1			T1	4		T4	1		T6	2
valid_sources[0x7d]	3161	1			T3	11		T4	1		T6	1
valid_sources[0x7e]	4080	1			T7	11		T9	13		T21	1
valid_sources[0x7f]	3271	1			T1	2		T4	1		T6	1
valid_sources[0x80]	3531	1			T1	1		T4	1		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

240154

1

T1

40

T3

132

T4

35

values[0x0]

all_enables

biggest_size

78233

1

T1

15

T3

55

T4

17

values[0x1]

all_enables

biggest_size

41608

1

T1

9

T3

27

T4

10