Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T7,T9,T21

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53482168	8169	0	0
CascadeEffAonToRstPorAboveRise_A	53482168	8169	0	0
CascadeEffAonToRstPorIoAboveFall_A	51340958	8169	0	0
CascadeEffAonToRstPorIoAboveRise_A	51340958	8169	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25671653	8169	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25671653	8169	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12835513	8169	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12835513	8169	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25671584	8169	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25671584	8169	0	0
CascadeLcToLcAboveFall_A	53482168	20877	0	0
CascadeLcToLcAboveRise_A	53482168	20877	0	0
CascadeLcToLcAonAboveFall_A	1620109	20877	0	0
CascadeLcToLcAonAboveRise_A	1620109	20877	0	0
CascadeLcToLcShadowedAboveFall_A	53482168	20877	0	0
CascadeLcToLcShadowedAboveRise_A	53482168	20877	0	0
CascadePorToAonAboveFall_A	1620109	6450	0	0
CascadeSysToSysAboveFall_A	53482168	20877	0	0
CascadeSysToSysAboveRise_A	53482168	20877	0	0
ScanRstToAonRise_A	1620109	201	0	0
StablePorToAonRise_A	1620109	8169	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11447584	20877	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11447584	20877	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11447584	20877	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11447584	20877	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12835513	20877	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12835513	20877	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11447584	20877	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11447584	20877	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11447584	20877	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11447584	20877	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	8169	0	0
T1	16439	2	0	0
T2	24245	8	0	0
T3	57276	7	0	0
T4	11141	2	0	0
T5	8680	2	0	0
T6	15626	1	0	0
T7	124743	15	0	0
T8	8764	2	0	0
T9	112594	23	0	0
T10	23612	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	8169	0	0
T1	16439	2	0	0
T2	24245	8	0	0
T3	57276	7	0	0
T4	11141	2	0	0
T5	8680	2	0	0
T6	15626	1	0	0
T7	124743	15	0	0
T8	8764	2	0	0
T9	112594	23	0	0
T10	23612	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51340958	8169	0	0
T1	15781	2	0	0
T2	23262	8	0	0
T3	55000	7	0	0
T4	10693	2	0	0
T5	8332	2	0	0
T6	15000	1	0	0
T7	119754	15	0	0
T8	8412	2	0	0
T9	108081	23	0	0
T10	22664	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51340958	8169	0	0
T1	15781	2	0	0
T2	23262	8	0	0
T3	55000	7	0	0
T4	10693	2	0	0
T5	8332	2	0	0
T6	15000	1	0	0
T7	119754	15	0	0
T8	8412	2	0	0
T9	108081	23	0	0
T10	22664	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671653	8169	0	0
T1	7891	2	0	0
T2	11635	8	0	0
T3	27493	7	0	0
T4	5347	2	0	0
T5	4166	2	0	0
T6	7500	1	0	0
T7	59885	15	0	0
T8	4207	2	0	0
T9	54046	23	0	0
T10	11335	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671653	8169	0	0
T1	7891	2	0	0
T2	11635	8	0	0
T3	27493	7	0	0
T4	5347	2	0	0
T5	4166	2	0	0
T6	7500	1	0	0
T7	59885	15	0	0
T8	4207	2	0	0
T9	54046	23	0	0
T10	11335	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	8169	0	0
T1	3943	2	0	0
T2	5819	8	0	0
T3	13748	7	0	0
T4	2675	2	0	0
T5	2083	2	0	0
T6	3749	1	0	0
T7	29937	15	0	0
T8	2102	2	0	0
T9	27017	23	0	0
T10	5665	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	8169	0	0
T1	3943	2	0	0
T2	5819	8	0	0
T3	13748	7	0	0
T4	2675	2	0	0
T5	2083	2	0	0
T6	3749	1	0	0
T7	29937	15	0	0
T8	2102	2	0	0
T9	27017	23	0	0
T10	5665	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671584	8169	0	0
T1	7890	2	0	0
T2	11636	8	0	0
T3	27497	7	0	0
T4	5348	2	0	0
T5	4166	2	0	0
T6	7499	1	0	0
T7	59880	15	0	0
T8	4206	2	0	0
T9	54044	23	0	0
T10	11331	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671584	8169	0	0
T1	7890	2	0	0
T2	11636	8	0	0
T3	27497	7	0	0
T4	5348	2	0	0
T5	4166	2	0	0
T6	7499	1	0	0
T7	59880	15	0	0
T8	4206	2	0	0
T9	54044	23	0	0
T10	11331	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	20877	0	0
T1	16439	6	0	0
T2	24245	8	0	0
T3	57276	19	0	0
T4	11141	6	0	0
T5	8680	2	0	0
T6	15626	20	0	0
T7	124743	49	0	0
T8	8764	2	0	0
T9	112594	63	0	0
T10	23612	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	20877	0	0
T1	16439	6	0	0
T2	24245	8	0	0
T3	57276	19	0	0
T4	11141	6	0	0
T5	8680	2	0	0
T6	15626	20	0	0
T7	124743	49	0	0
T8	8764	2	0	0
T9	112594	63	0	0
T10	23612	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	20877	0	0
T1	491	6	0	0
T2	729	8	0	0
T3	1718	19	0	0
T4	333	6	0	0
T5	259	2	0	0
T6	468	20	0	0
T7	3808	49	0	0
T8	261	2	0	0
T9	3418	63	0	0
T10	706	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	20877	0	0
T1	491	6	0	0
T2	729	8	0	0
T3	1718	19	0	0
T4	333	6	0	0
T5	259	2	0	0
T6	468	20	0	0
T7	3808	49	0	0
T8	261	2	0	0
T9	3418	63	0	0
T10	706	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	20877	0	0
T1	16439	6	0	0
T2	24245	8	0	0
T3	57276	19	0	0
T4	11141	6	0	0
T5	8680	2	0	0
T6	15626	20	0	0
T7	124743	49	0	0
T8	8764	2	0	0
T9	112594	63	0	0
T10	23612	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	20877	0	0
T1	16439	6	0	0
T2	24245	8	0	0
T3	57276	19	0	0
T4	11141	6	0	0
T5	8680	2	0	0
T6	15626	20	0	0
T7	124743	49	0	0
T8	8764	2	0	0
T9	112594	63	0	0
T10	23612	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	6450	0	0
T1	491	1	0	0
T2	729	8	0	0
T3	1718	4	0	0
T4	333	1	0	0
T5	259	2	0	0
T6	468	1	0	0
T7	3808	7	0	0
T8	261	2	0	0
T9	3418	17	0	0
T10	706	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	20877	0	0
T1	16439	6	0	0
T2	24245	8	0	0
T3	57276	19	0	0
T4	11141	6	0	0
T5	8680	2	0	0
T6	15626	20	0	0
T7	124743	49	0	0
T8	8764	2	0	0
T9	112594	63	0	0
T10	23612	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53482168	20877	0	0
T1	16439	6	0	0
T2	24245	8	0	0
T3	57276	19	0	0
T4	11141	6	0	0
T5	8680	2	0	0
T6	15626	20	0	0
T7	124743	49	0	0
T8	8764	2	0	0
T9	112594	63	0	0
T10	23612	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	201	0	0
T3	1718	1	0	0
T4	333	0	0	0
T5	259	0	0	0
T6	468	0	0	0
T7	3808	0	0	0
T8	261	0	0	0
T9	3418	0	0	0
T10	706	0	0	0
T11	294	1	0	0
T20	1599	0	0	0
T34	0	2	0	0
T48	0	1	0	0
T53	0	5	0	0
T78	0	6	0	0
T91	0	7	0	0
T92	0	2	0	0
T123	0	1	0	0
T124	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	8169	0	0
T1	491	2	0	0
T2	729	8	0	0
T3	1718	7	0	0
T4	333	2	0	0
T5	259	2	0	0
T6	468	1	0	0
T7	3808	15	0	0
T8	261	2	0	0
T9	3418	23	0	0
T10	706	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	20877	0	0
T1	3943	6	0	0
T2	5819	8	0	0
T3	13748	19	0	0
T4	2675	6	0	0
T5	2083	2	0	0
T6	3749	20	0	0
T7	29937	49	0	0
T8	2102	2	0	0
T9	27017	63	0	0
T10	5665	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	20877	0	0
T1	3943	6	0	0
T2	5819	8	0	0
T3	13748	19	0	0
T4	2675	6	0	0
T5	2083	2	0	0
T6	3749	20	0	0
T7	29937	49	0	0
T8	2102	2	0	0
T9	27017	63	0	0
T10	5665	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11447584	20877	0	0
T1	3799	6	0	0
T2	5464	8	0	0
T3	13121	19	0	0
T4	2385	6	0	0
T5	1968	2	0	0
T6	2418	20	0	0
T7	25335	49	0	0
T8	1964	2	0	0
T9	20588	63	0	0
T10	5521	6	0	0