Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T10,T20
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T20,T60
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T20,T53
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T20,T60
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T53,T54
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T20,T53
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T62,T63
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T60,T53
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12835513	13669	0	0
gen_assertions[0].RstEnOn_A	12835513	1140	0	0
gen_assertions[0].RstNOff_A	12835513	13669	0	0
gen_assertions[0].RstNOn_A	12835513	1140	0	0
gen_assertions[1].RstEnOff_A	51340958	12391	0	0
gen_assertions[1].RstEnOn_A	51340958	1058	0	0
gen_assertions[1].RstNOff_A	51340958	12391	0	0
gen_assertions[1].RstNOn_A	51340958	1058	0	0
gen_assertions[2].RstEnOff_A	25671653	12477	0	0
gen_assertions[2].RstEnOn_A	25671653	1092	0	0
gen_assertions[2].RstNOff_A	25671653	12477	0	0
gen_assertions[2].RstNOn_A	25671653	1092	0	0
gen_assertions[3].RstEnOff_A	25671584	12520	0	0
gen_assertions[3].RstEnOn_A	25671584	1144	0	0
gen_assertions[3].RstNOff_A	25671584	12520	0	0
gen_assertions[3].RstNOn_A	25671584	1144	0	0
gen_assertions[4].RstEnOff_A	1620109	20816	0	0
gen_assertions[4].RstEnOn_A	1620109	1209	0	0
gen_assertions[4].RstNOff_A	1620109	20816	0	0
gen_assertions[4].RstNOn_A	1620109	1209	0	0
gen_assertions[5].RstEnOff_A	12835513	13905	0	0
gen_assertions[5].RstEnOn_A	12835513	1242	0	0
gen_assertions[5].RstNOff_A	12835513	13905	0	0
gen_assertions[5].RstNOn_A	12835513	1242	0	0
gen_assertions[6].RstEnOff_A	12835513	13951	0	0
gen_assertions[6].RstEnOn_A	12835513	1285	0	0
gen_assertions[6].RstNOff_A	12835513	13951	0	0
gen_assertions[6].RstNOn_A	12835513	1285	0	0
gen_assertions[7].RstEnOff_A	12835513	13985	0	0
gen_assertions[7].RstEnOn_A	12835513	1312	0	0
gen_assertions[7].RstNOff_A	12835513	13985	0	0
gen_assertions[7].RstNOn_A	12835513	1312	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13669	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	5	0	0
T11	0	4	0	0
T20	0	9	0	0
T21	0	30	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1140	0	0
T6	3749	8	0	0
T7	29937	0	0	0
T8	2102	0	0	0
T9	27017	0	0	0
T10	5665	1	0	0
T11	2364	0	0	0
T20	12802	9	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T52	0	2	0	0
T53	0	15	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T74	1638	0	0	0
T77	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13669	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	5	0	0
T11	0	4	0	0
T20	0	9	0	0
T21	0	30	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1140	0	0
T6	3749	8	0	0
T7	29937	0	0	0
T8	2102	0	0	0
T9	27017	0	0	0
T10	5665	1	0	0
T11	2364	0	0	0
T20	12802	9	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T52	0	2	0	0
T53	0	15	0	0
T59	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T74	1638	0	0	0
T77	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51340958	12391	0	0
T1	15781	3	0	0
T2	23262	0	0	0
T3	55000	11	0	0
T4	10693	4	0	0
T5	8332	0	0	0
T6	15000	18	0	0
T7	119754	32	0	0
T8	8412	0	0	0
T9	108081	33	0	0
T10	22664	4	0	0
T11	0	3	0	0
T20	0	8	0	0
T21	0	26	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51340958	1058	0	0
T6	15000	5	0	0
T7	119754	0	0	0
T8	8412	0	0	0
T9	108081	0	0	0
T10	22664	0	0	0
T11	9460	0	0	0
T20	51215	8	0	0
T21	137465	0	0	0
T22	6736	0	0	0
T53	0	13	0	0
T54	0	3	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	9	0	0
T74	6558	0	0	0
T77	0	1	0	0
T78	0	18	0	0
T79	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51340958	12391	0	0
T1	15781	3	0	0
T2	23262	0	0	0
T3	55000	11	0	0
T4	10693	4	0	0
T5	8332	0	0	0
T6	15000	18	0	0
T7	119754	32	0	0
T8	8412	0	0	0
T9	108081	33	0	0
T10	22664	4	0	0
T11	0	3	0	0
T20	0	8	0	0
T21	0	26	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51340958	1058	0	0
T6	15000	5	0	0
T7	119754	0	0	0
T8	8412	0	0	0
T9	108081	0	0	0
T10	22664	0	0	0
T11	9460	0	0	0
T20	51215	8	0	0
T21	137465	0	0	0
T22	6736	0	0	0
T53	0	13	0	0
T54	0	3	0	0
T60	0	1	0	0
T62	0	1	0	0
T65	0	9	0	0
T74	6558	0	0	0
T77	0	1	0	0
T78	0	18	0	0
T79	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671653	12477	0	0
T1	7891	3	0	0
T2	11635	0	0	0
T3	27493	11	0	0
T4	5347	4	0	0
T5	4166	0	0	0
T6	7500	18	0	0
T7	59885	32	0	0
T8	4207	0	0	0
T9	54046	33	0	0
T10	11335	5	0	0
T11	0	3	0	0
T20	0	10	0	0
T21	0	26	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671653	1092	0	0
T10	11335	1	0	0
T11	4729	0	0	0
T20	25607	10	0	0
T21	68737	0	0	0
T22	3368	0	0	0
T44	0	7	0	0
T45	0	8	0	0
T46	0	4	0	0
T50	3410	0	0	0
T51	422678	0	0	0
T53	0	13	0	0
T54	0	2	0	0
T56	58463	0	0	0
T59	9329	0	0	0
T65	0	8	0	0
T74	3279	0	0	0
T78	0	19	0	0
T79	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671653	12477	0	0
T1	7891	3	0	0
T2	11635	0	0	0
T3	27493	11	0	0
T4	5347	4	0	0
T5	4166	0	0	0
T6	7500	18	0	0
T7	59885	32	0	0
T8	4207	0	0	0
T9	54046	33	0	0
T10	11335	5	0	0
T11	0	3	0	0
T20	0	10	0	0
T21	0	26	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671653	1092	0	0
T10	11335	1	0	0
T11	4729	0	0	0
T20	25607	10	0	0
T21	68737	0	0	0
T22	3368	0	0	0
T44	0	7	0	0
T45	0	8	0	0
T46	0	4	0	0
T50	3410	0	0	0
T51	422678	0	0	0
T53	0	13	0	0
T54	0	2	0	0
T56	58463	0	0	0
T59	9329	0	0	0
T65	0	8	0	0
T74	3279	0	0	0
T78	0	19	0	0
T79	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671584	12520	0	0
T1	7890	3	0	0
T2	11636	0	0	0
T3	27497	11	0	0
T4	5348	4	0	0
T5	4166	0	0	0
T6	7499	18	0	0
T7	59880	32	0	0
T8	4206	0	0	0
T9	54044	33	0	0
T10	11331	5	0	0
T11	0	3	0	0
T20	0	10	0	0
T21	0	26	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671584	1144	0	0
T10	11331	1	0	0
T11	4732	0	0	0
T20	25607	10	0	0
T21	68727	0	0	0
T22	3368	0	0	0
T44	0	11	0	0
T50	3410	0	0	0
T51	422675	0	0	0
T53	0	13	0	0
T54	0	2	0	0
T56	58456	0	0	0
T59	9329	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T65	0	9	0	0
T74	3278	0	0	0
T78	0	20	0	0
T79	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671584	12520	0	0
T1	7890	3	0	0
T2	11636	0	0	0
T3	27497	11	0	0
T4	5348	4	0	0
T5	4166	0	0	0
T6	7499	18	0	0
T7	59880	32	0	0
T8	4206	0	0	0
T9	54044	33	0	0
T10	11331	5	0	0
T11	0	3	0	0
T20	0	10	0	0
T21	0	26	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25671584	1144	0	0
T10	11331	1	0	0
T11	4732	0	0	0
T20	25607	10	0	0
T21	68727	0	0	0
T22	3368	0	0	0
T44	0	11	0	0
T50	3410	0	0	0
T51	422675	0	0	0
T53	0	13	0	0
T54	0	2	0	0
T56	58456	0	0	0
T59	9329	0	0	0
T60	0	1	0	0
T63	0	1	0	0
T65	0	9	0	0
T74	3278	0	0	0
T78	0	20	0	0
T79	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	20816	0	0
T1	491	6	0	0
T2	729	3	0	0
T3	1718	18	0	0
T4	333	5	0	0
T5	259	2	0	0
T6	468	19	0	0
T7	3808	49	0	0
T8	261	2	0	0
T9	3418	63	0	0
T10	706	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	1209	0	0
T20	1599	8	0	0
T21	4325	0	0	0
T22	210	0	0	0
T44	0	9	0	0
T45	0	11	0	0
T46	0	6	0	0
T49	0	9	0	0
T50	212	0	0	0
T51	26538	0	0	0
T53	0	17	0	0
T54	0	3	0	0
T56	3668	0	0	0
T59	582	0	0	0
T60	728	0	0	0
T61	456	0	0	0
T65	0	10	0	0
T74	204	0	0	0
T78	0	20	0	0
T79	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	20816	0	0
T1	491	6	0	0
T2	729	3	0	0
T3	1718	18	0	0
T4	333	5	0	0
T5	259	2	0	0
T6	468	19	0	0
T7	3808	49	0	0
T8	261	2	0	0
T9	3418	63	0	0
T10	706	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1620109	1209	0	0
T20	1599	8	0	0
T21	4325	0	0	0
T22	210	0	0	0
T44	0	9	0	0
T45	0	11	0	0
T46	0	6	0	0
T49	0	9	0	0
T50	212	0	0	0
T51	26538	0	0	0
T53	0	17	0	0
T54	0	3	0	0
T56	3668	0	0	0
T59	582	0	0	0
T60	728	0	0	0
T61	456	0	0	0
T65	0	10	0	0
T74	204	0	0	0
T78	0	20	0	0
T79	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13905	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	5	0	0
T11	0	4	0	0
T20	0	11	0	0
T21	0	30	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1242	0	0
T10	5665	1	0	0
T11	2364	0	0	0
T20	12802	11	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T44	0	12	0	0
T45	0	13	0	0
T46	0	7	0	0
T50	1704	0	0	0
T51	211333	0	0	0
T53	0	15	0	0
T54	0	3	0	0
T56	29231	0	0	0
T59	4664	0	0	0
T65	0	9	0	0
T74	1638	0	0	0
T78	0	17	0	0
T79	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13905	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	5	0	0
T11	0	4	0	0
T20	0	11	0	0
T21	0	30	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1242	0	0
T10	5665	1	0	0
T11	2364	0	0	0
T20	12802	11	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T44	0	12	0	0
T45	0	13	0	0
T46	0	7	0	0
T50	1704	0	0	0
T51	211333	0	0	0
T53	0	15	0	0
T54	0	3	0	0
T56	29231	0	0	0
T59	4664	0	0	0
T65	0	9	0	0
T74	1638	0	0	0
T78	0	17	0	0
T79	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13951	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	4	0	0
T11	0	4	0	0
T20	0	12	0	0
T21	0	30	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1285	0	0
T20	12802	12	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T44	0	12	0	0
T45	0	12	0	0
T50	1704	0	0	0
T51	211333	0	0	0
T53	0	17	0	0
T54	0	3	0	0
T56	29231	0	0	0
T59	4664	0	0	0
T60	5839	0	0	0
T61	3656	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	12	0	0
T74	1638	0	0	0
T78	0	16	0	0
T79	0	4	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13951	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	4	0	0
T11	0	4	0	0
T20	0	12	0	0
T21	0	30	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1285	0	0
T20	12802	12	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T44	0	12	0	0
T45	0	12	0	0
T50	1704	0	0	0
T51	211333	0	0	0
T53	0	17	0	0
T54	0	3	0	0
T56	29231	0	0	0
T59	4664	0	0	0
T60	5839	0	0	0
T61	3656	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T65	0	12	0	0
T74	1638	0	0	0
T78	0	16	0	0
T79	0	4	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13985	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	4	0	0
T11	0	4	0	0
T20	0	13	0	0
T21	0	30	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1312	0	0
T20	12802	13	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T44	0	13	0	0
T45	0	16	0	0
T46	0	9	0	0
T50	1704	0	0	0
T51	211333	0	0	0
T53	0	15	0	0
T54	0	3	0	0
T56	29231	0	0	0
T59	4664	0	0	0
T60	5839	1	0	0
T61	3656	0	0	0
T65	0	15	0	0
T74	1638	0	0	0
T78	0	13	0	0
T79	0	3	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	13985	0	0
T1	3943	4	0	0
T2	5819	0	0	0
T3	13748	12	0	0
T4	2675	4	0	0
T5	2083	0	0	0
T6	3749	19	0	0
T7	29937	34	0	0
T8	2102	0	0	0
T9	27017	40	0	0
T10	5665	4	0	0
T11	0	4	0	0
T20	0	13	0	0
T21	0	30	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12835513	1312	0	0
T20	12802	13	0	0
T21	34368	0	0	0
T22	1684	0	0	0
T44	0	13	0	0
T45	0	16	0	0
T46	0	9	0	0
T50	1704	0	0	0
T51	211333	0	0	0
T53	0	15	0	0
T54	0	3	0	0
T56	29231	0	0	0
T59	4664	0	0	0
T60	5839	1	0	0
T61	3656	0	0	0
T65	0	15	0	0
T74	1638	0	0	0
T78	0	13	0	0
T79	0	3	0	0