Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12188270	7124	0	0
alert_regwen_rd_A	12188270	5512	0	0
cpu_regwen_rd_A	12188270	5313	0	0
sw_rst_ctrl_n_0_rd_A	12188270	10809	0	0
sw_rst_ctrl_n_1_rd_A	12188270	10737	0	0
sw_rst_ctrl_n_2_rd_A	12188270	10954	0	0
sw_rst_ctrl_n_3_rd_A	12188270	10521	0	0
sw_rst_ctrl_n_4_rd_A	12188270	10741	0	0
sw_rst_ctrl_n_5_rd_A	12188270	10577	0	0
sw_rst_ctrl_n_6_rd_A	12188270	10769	0	0
sw_rst_ctrl_n_7_rd_A	12188270	10728	0	0
sw_rst_regwen_0_rd_A	12188270	5726	0	0
sw_rst_regwen_1_rd_A	12188270	5679	0	0
sw_rst_regwen_2_rd_A	12188270	5897	0	0
sw_rst_regwen_3_rd_A	12188270	5762	0	0
sw_rst_regwen_4_rd_A	12188270	5907	0	0
sw_rst_regwen_5_rd_A	12188270	6022	0	0
sw_rst_regwen_6_rd_A	12188270	5926	0	0
sw_rst_regwen_7_rd_A	12188270	5873	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	7124	0	0
T67	2333	56	0	0
T69	20993	3	0	0
T70	2358	28	0	0
T71	14481	618	0	0
T72	4677	511	0	0
T81	4377	18	0	0
T82	7712	223	0	0
T83	2831	396	0	0
T87	20723	3	0	0
T88	10639	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5512	0	0
T21	30040	55	0	0
T22	1562	0	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	5647	0	0	0
T61	3416	0	0	0
T62	5383	0	0	0
T74	1596	0	0	0
T78	0	297	0	0
T79	0	56	0	0
T91	0	517	0	0
T96	0	221	0	0
T97	0	69	0	0
T116	0	45	0	0
T117	0	282	0	0
T118	0	269	0	0
T119	0	75	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5313	0	0
T21	30040	55	0	0
T22	1562	0	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	5647	0	0	0
T61	3416	0	0	0
T62	5383	0	0	0
T74	1596	0	0	0
T78	0	246	0	0
T79	0	52	0	0
T91	0	497	0	0
T96	0	284	0	0
T97	0	61	0	0
T116	0	41	0	0
T117	0	301	0	0
T118	0	221	0	0
T119	0	55	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10809	0	0
T10	5521	9	0	0
T11	2122	0	0	0
T20	12737	204	0	0
T21	30040	43	0	0
T22	1562	6	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	20	0	0
T56	26232	0	0	0
T59	3818	45	0	0
T60	0	11	0	0
T62	0	12	0	0
T74	1596	0	0	0
T78	0	528	0	0
T79	0	128	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10737	0	0
T10	5521	15	0	0
T11	2122	0	0	0
T20	12737	239	0	0
T21	30040	44	0	0
T22	1562	5	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	24	0	0
T56	26232	0	0	0
T59	3818	34	0	0
T60	0	22	0	0
T62	0	13	0	0
T74	1596	0	0	0
T78	0	490	0	0
T79	0	102	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10954	0	0
T10	5521	10	0	0
T11	2122	0	0	0
T20	12737	185	0	0
T21	30040	54	0	0
T22	1562	2	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	31	0	0
T56	26232	0	0	0
T59	3818	38	0	0
T60	0	15	0	0
T62	0	2	0	0
T74	1596	0	0	0
T78	0	543	0	0
T79	0	123	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10521	0	0
T10	5521	7	0	0
T11	2122	0	0	0
T20	12737	196	0	0
T21	30040	49	0	0
T22	1562	4	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	36	0	0
T56	26232	0	0	0
T59	3818	41	0	0
T60	0	21	0	0
T62	0	13	0	0
T74	1596	0	0	0
T78	0	465	0	0
T79	0	103	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10741	0	0
T20	12737	221	0	0
T21	30040	34	0	0
T22	1562	3	0	0
T45	0	195	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	25	0	0
T56	26232	0	0	0
T59	3818	35	0	0
T60	5647	6	0	0
T61	3416	0	0	0
T62	0	15	0	0
T74	1596	0	0	0
T78	0	488	0	0
T79	0	91	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10577	0	0
T10	5521	14	0	0
T11	2122	0	0	0
T20	12737	203	0	0
T21	30040	38	0	0
T22	1562	4	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	19	0	0
T56	26232	0	0	0
T59	3818	45	0	0
T60	0	9	0	0
T62	0	1	0	0
T74	1596	0	0	0
T78	0	491	0	0
T79	0	112	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10769	0	0
T10	5521	18	0	0
T11	2122	0	0	0
T20	12737	229	0	0
T21	30040	48	0	0
T22	1562	7	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	15	0	0
T56	26232	0	0	0
T59	3818	42	0	0
T60	0	13	0	0
T62	0	6	0	0
T74	1596	0	0	0
T78	0	526	0	0
T79	0	96	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	10728	0	0
T10	5521	11	0	0
T11	2122	0	0	0
T20	12737	213	0	0
T21	30040	38	0	0
T22	1562	2	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T52	0	21	0	0
T56	26232	0	0	0
T59	3818	30	0	0
T60	0	13	0	0
T62	0	10	0	0
T74	1596	0	0	0
T78	0	487	0	0
T79	0	95	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5726	0	0
T10	5521	6	0	0
T11	2122	0	0	0
T20	12737	37	0	0
T21	30040	46	0	0
T22	1562	0	0	0
T45	0	27	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	0	12	0	0
T62	0	5	0	0
T74	1596	0	0	0
T78	0	258	0	0
T79	0	44	0	0
T91	0	512	0	0
T120	0	25	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5679	0	0
T10	5521	1	0	0
T11	2122	0	0	0
T20	12737	27	0	0
T21	30040	54	0	0
T22	1562	0	0	0
T45	0	42	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	0	10	0	0
T74	1596	0	0	0
T78	0	240	0	0
T79	0	56	0	0
T91	0	494	0	0
T120	0	39	0	0
T121	0	20	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5897	0	0
T10	5521	12	0	0
T11	2122	0	0	0
T20	12737	22	0	0
T21	30040	59	0	0
T22	1562	0	0	0
T45	0	38	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	0	6	0	0
T74	1596	0	0	0
T78	0	268	0	0
T79	0	44	0	0
T91	0	519	0	0
T120	0	22	0	0
T121	0	10	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5762	0	0
T10	5521	3	0	0
T11	2122	0	0	0
T20	12737	31	0	0
T21	30040	17	0	0
T22	1562	0	0	0
T45	0	46	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	0	11	0	0
T62	0	2	0	0
T74	1596	0	0	0
T78	0	267	0	0
T79	0	57	0	0
T91	0	499	0	0
T120	0	24	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5907	0	0
T20	12737	25	0	0
T21	30040	56	0	0
T22	1562	0	0	0
T45	0	41	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	5647	5	0	0
T61	3416	0	0	0
T74	1596	0	0	0
T78	0	294	0	0
T79	0	31	0	0
T91	0	508	0	0
T120	0	34	0	0
T121	0	20	0	0
T122	0	36	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	6022	0	0
T10	5521	5	0	0
T11	2122	0	0	0
T20	12737	45	0	0
T21	30040	57	0	0
T22	1562	0	0	0
T45	0	31	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	0	1	0	0
T62	0	8	0	0
T74	1596	0	0	0
T78	0	243	0	0
T79	0	52	0	0
T91	0	500	0	0
T120	0	32	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5926	0	0
T10	5521	8	0	0
T11	2122	0	0	0
T20	12737	30	0	0
T21	30040	54	0	0
T22	1562	0	0	0
T45	0	20	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	0	7	0	0
T62	0	7	0	0
T74	1596	0	0	0
T78	0	274	0	0
T79	0	52	0	0
T91	0	557	0	0
T120	0	28	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12188270	5873	0	0
T20	12737	32	0	0
T21	30040	30	0	0
T22	1562	0	0	0
T45	0	38	0	0
T50	1638	0	0	0
T51	199313	0	0	0
T56	26232	0	0	0
T59	3818	0	0	0
T60	5647	12	0	0
T61	3416	0	0	0
T74	1596	0	0	0
T78	0	299	0	0
T79	0	55	0	0
T91	0	547	0	0
T120	0	20	0	0
T121	0	14	0	0
T122	0	8	0	0