Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	608052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

367569

1

T2

1076

T3

1

T4

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	520899	1			T2	1500		T4	73		T6	99
values[0x0]	227182	1			T2	864		T3	2		T4	40
values[0x1]	227540	1			T2	836		T3	6		T4	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	510074	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

465547

1

T2

1409

T3

2

T4

69

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3330	1			T3	1		T7	11		T8	5
valid_sources[0x01]	3382	1			T8	1		T9	8		T11	4
valid_sources[0x02]	6931	1			T7	31		T8	2		T9	13
valid_sources[0x03]	3151	1			T7	24		T8	3		T9	22
valid_sources[0x04]	3273	1			T7	11		T8	3		T9	11
valid_sources[0x05]	4165	1			T7	25		T9	12		T10	1
valid_sources[0x06]	3662	1			T7	32		T8	4		T9	19
valid_sources[0x07]	3006	1			T7	34		T8	2		T9	8
valid_sources[0x08]	4378	1			T6	6		T7	12		T8	1
valid_sources[0x09]	6562	1			T2	3200		T6	1		T7	5
valid_sources[0x0a]	3249	1			T7	17		T8	2		T9	14
valid_sources[0x0b]	4040	1			T7	2		T8	4		T9	16
valid_sources[0x0c]	6776	1			T7	5		T8	3		T9	11
valid_sources[0x0d]	3627	1			T7	4		T8	4		T9	13
valid_sources[0x0e]	3894	1			T7	1		T8	2		T9	12
valid_sources[0x0f]	2995	1			T7	27		T8	3		T9	7
valid_sources[0x10]	3143	1			T7	2		T8	2		T9	7
valid_sources[0x11]	3366	1			T6	22		T7	13		T9	15
valid_sources[0x12]	4199	1			T7	11		T9	15		T15	73
valid_sources[0x13]	3247	1			T7	2		T8	2		T9	20
valid_sources[0x14]	3196	1			T7	29		T8	4		T9	13
valid_sources[0x15]	3763	1			T7	25		T8	3		T9	6
valid_sources[0x16]	4433	1			T7	32		T8	7		T9	13
valid_sources[0x17]	3729	1			T7	3		T8	2		T9	14
valid_sources[0x18]	4671	1			T7	5		T8	2		T9	11
valid_sources[0x19]	4379	1			T7	9		T8	6		T9	7
valid_sources[0x1a]	3298	1			T7	14		T8	7		T9	8
valid_sources[0x1b]	3722	1			T7	21		T9	11		T11	3
valid_sources[0x1c]	3638	1			T7	6		T8	3		T9	12
valid_sources[0x1d]	3640	1			T7	34		T8	4		T9	17
valid_sources[0x1e]	4196	1			T7	13		T8	1		T9	14
valid_sources[0x1f]	3404	1			T7	5		T8	4		T9	12
valid_sources[0x20]	3175	1			T7	10		T8	1		T9	12
valid_sources[0x21]	3638	1			T7	5		T8	1		T9	14
valid_sources[0x22]	3812	1			T7	9		T8	3		T9	18
valid_sources[0x23]	3514	1			T7	15		T8	5		T9	12
valid_sources[0x24]	3078	1			T7	1		T8	1		T9	6
valid_sources[0x25]	3935	1			T7	21		T8	4		T9	13
valid_sources[0x26]	3801	1			T7	34		T8	2		T9	19
valid_sources[0x27]	6835	1			T7	7		T8	3		T9	15
valid_sources[0x28]	3236	1			T7	4		T8	3		T9	17
valid_sources[0x29]	3254	1			T7	4		T8	5		T9	13
valid_sources[0x2a]	3318	1			T7	11		T8	3		T9	9
valid_sources[0x2b]	3218	1			T7	1		T8	2		T9	10
valid_sources[0x2c]	3736	1			T7	20		T8	1		T9	8
valid_sources[0x2d]	3608	1			T7	6		T8	3		T9	12
valid_sources[0x2e]	3516	1			T7	2		T9	13		T11	6
valid_sources[0x2f]	3237	1			T7	6		T8	1		T9	10
valid_sources[0x30]	3927	1			T7	20		T8	4		T9	11
valid_sources[0x31]	3504	1			T7	54		T8	4		T9	19
valid_sources[0x32]	4315	1			T7	1		T8	2		T9	16
valid_sources[0x33]	4062	1			T7	5		T8	6		T9	6
valid_sources[0x34]	3424	1			T7	8		T8	1		T9	18
valid_sources[0x35]	3556	1			T7	5		T8	4		T9	15
valid_sources[0x36]	3809	1			T7	24		T8	5		T9	12
valid_sources[0x37]	3156	1			T7	17		T8	3		T9	13
valid_sources[0x38]	3422	1			T6	17		T7	9		T8	2
valid_sources[0x39]	3879	1			T7	22		T8	4		T9	17
valid_sources[0x3a]	3440	1			T7	4		T8	3		T9	7
valid_sources[0x3b]	3717	1			T7	7		T8	1		T9	14
valid_sources[0x3c]	4060	1			T7	6		T8	2		T9	14
valid_sources[0x3d]	3570	1			T7	17		T8	6		T9	10
valid_sources[0x3e]	5213	1			T7	2		T8	2		T9	8
valid_sources[0x3f]	3140	1			T7	10		T8	2		T9	12
valid_sources[0x40]	3630	1			T7	8		T8	2		T9	12
valid_sources[0x41]	3770	1			T7	24		T8	3		T9	9
valid_sources[0x42]	3598	1			T7	5		T8	6		T9	16
valid_sources[0x43]	3169	1			T7	5		T8	3		T9	12
valid_sources[0x44]	3388	1			T7	11		T8	2		T9	12
valid_sources[0x45]	3734	1			T7	10		T8	3		T9	12
valid_sources[0x46]	3437	1			T7	9		T8	3		T9	17
valid_sources[0x47]	3464	1			T7	1		T8	6		T9	14
valid_sources[0x48]	3384	1			T9	13		T15	52		T60	11
valid_sources[0x49]	4898	1			T7	20		T8	5		T9	14
valid_sources[0x4a]	3501	1			T7	47		T8	4		T9	10
valid_sources[0x4b]	3632	1			T7	9		T8	1		T9	15
valid_sources[0x4c]	3462	1			T7	1		T8	5		T9	10
valid_sources[0x4d]	3374	1			T7	8		T8	2		T9	6
valid_sources[0x4e]	4407	1			T7	3		T8	2		T9	16
valid_sources[0x4f]	3324	1			T7	29		T8	1		T9	15
valid_sources[0x50]	3921	1			T7	16		T8	3		T9	13
valid_sources[0x51]	4019	1			T7	1		T8	1		T9	7
valid_sources[0x52]	3173	1			T6	13		T7	19		T8	5
valid_sources[0x53]	3493	1			T7	11		T8	1		T9	16
valid_sources[0x54]	3422	1			T8	1		T9	18		T11	2
valid_sources[0x55]	3373	1			T7	6		T8	4		T9	8
valid_sources[0x56]	3480	1			T7	17		T8	3		T9	14
valid_sources[0x57]	3064	1			T3	2		T7	1		T9	15
valid_sources[0x58]	3227	1			T7	11		T8	2		T9	15
valid_sources[0x59]	4248	1			T7	7		T8	2		T9	11
valid_sources[0x5a]	3773	1			T7	14		T9	17		T15	68
valid_sources[0x5b]	3411	1			T7	6		T8	5		T9	7
valid_sources[0x5c]	3458	1			T7	10		T8	4		T9	15
valid_sources[0x5d]	4310	1			T7	26		T9	12		T15	49
valid_sources[0x5e]	4020	1			T7	9		T8	1		T9	13
valid_sources[0x5f]	4819	1			T3	1		T4	150		T7	1
valid_sources[0x60]	3532	1			T8	2		T9	11		T11	1
valid_sources[0x61]	3269	1			T7	1		T8	2		T9	13
valid_sources[0x62]	3096	1			T7	27		T8	4		T9	9
valid_sources[0x63]	3677	1			T7	20		T9	16		T11	1
valid_sources[0x64]	3714	1			T8	3		T9	11		T15	69
valid_sources[0x65]	3700	1			T8	3		T9	11		T11	3
valid_sources[0x66]	6821	1			T8	1		T9	9		T15	84
valid_sources[0x67]	3650	1			T7	2		T8	3		T9	18
valid_sources[0x68]	3457	1			T7	7		T8	1		T9	13
valid_sources[0x69]	3583	1			T7	11		T8	5		T9	11
valid_sources[0x6a]	3039	1			T7	7		T8	4		T9	16
valid_sources[0x6b]	3842	1			T7	7		T8	3		T9	4
valid_sources[0x6c]	4093	1			T7	34		T8	3		T9	15
valid_sources[0x6d]	4996	1			T7	5		T8	2		T9	16
valid_sources[0x6e]	2969	1			T9	14		T15	62		T60	4
valid_sources[0x6f]	3502	1			T7	3		T8	4		T9	15
valid_sources[0x70]	4692	1			T7	23		T8	1		T9	5
valid_sources[0x71]	3777	1			T7	4		T8	3		T9	7
valid_sources[0x72]	3799	1			T7	18		T8	2		T9	15
valid_sources[0x73]	3877	1			T7	14		T8	1		T9	14
valid_sources[0x74]	3327	1			T8	5		T9	17		T11	2
valid_sources[0x75]	4328	1			T7	5		T8	2		T9	7
valid_sources[0x76]	4151	1			T6	17		T8	5		T9	11
valid_sources[0x77]	4939	1			T7	9		T8	2		T9	16
valid_sources[0x78]	4083	1			T7	1		T8	3		T9	11
valid_sources[0x79]	3654	1			T7	15		T8	1		T9	11
valid_sources[0x7a]	4154	1			T7	35		T8	1		T9	13
valid_sources[0x7b]	3777	1			T7	33		T8	3		T9	11
valid_sources[0x7c]	4503	1			T7	13		T8	1		T9	8
valid_sources[0x7d]	3612	1			T7	8		T8	1		T9	17
valid_sources[0x7e]	3055	1			T7	8		T8	6		T9	20
valid_sources[0x7f]	3506	1			T7	13		T8	1		T9	11
valid_sources[0x80]	3901	1			T7	14		T8	4		T9	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

245194

1

T2

668

T4

41

T6

47

values[0x0]

all_enables

biggest_size

79469

1

T2

281

T4

11

T6

16

values[0x1]

all_enables

biggest_size

42906

1

T2

127

T3

1

T4

4