Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11217590	12946	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11217590	119289	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11217590	6566788	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11217590	190667	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11217590	12946	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11217590	119289	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11217590	6566788	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11217590	190667	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	12946	0	0
T2	26013	75	0	0
T3	1861	0	0	0
T4	2662	8	0	0
T5	5702	0	0	0
T6	2336	4	0	0
T7	42310	75	0	0
T8	2647	0	0	0
T9	26089	75	0	0
T10	179080	0	0	0
T11	4536	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0
T15	0	200	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	119289	0	0
T2	26013	718	0	0
T3	1861	0	0	0
T4	2662	72	0	0
T5	5702	0	0	0
T6	2336	38	0	0
T7	42310	703	0	0
T8	2647	0	0	0
T9	26089	709	0	0
T10	179080	0	0	0
T11	4536	171	0	0
T12	0	180	0	0
T13	0	326	0	0
T14	0	135	0	0
T15	0	1819	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	6566788	0	0
T1	5507	592	0	0
T2	26013	8751	0	0
T3	1861	1266	0	0
T4	2662	1897	0	0
T5	5702	576	0	0
T6	2336	1409	0	0
T7	42310	24676	0	0
T8	2647	2072	0	0
T9	26089	8706	0	0
T10	179080	19649	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	190667	0	0
T2	26013	1135	0	0
T3	1861	0	0	0
T4	2662	118	0	0
T5	5702	0	0	0
T6	2336	49	0	0
T7	42310	1097	0	0
T8	2647	0	0	0
T9	26089	1167	0	0
T10	179080	0	0	0
T11	4536	278	0	0
T12	0	300	0	0
T13	0	525	0	0
T14	0	229	0	0
T15	0	2932	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	12946	0	0
T2	26013	75	0	0
T3	1861	0	0	0
T4	2662	8	0	0
T5	5702	0	0	0
T6	2336	4	0	0
T7	42310	75	0	0
T8	2647	0	0	0
T9	26089	75	0	0
T10	179080	0	0	0
T11	4536	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0
T15	0	200	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	119289	0	0
T2	26013	718	0	0
T3	1861	0	0	0
T4	2662	72	0	0
T5	5702	0	0	0
T6	2336	38	0	0
T7	42310	703	0	0
T8	2647	0	0	0
T9	26089	709	0	0
T10	179080	0	0	0
T11	4536	171	0	0
T12	0	180	0	0
T13	0	326	0	0
T14	0	135	0	0
T15	0	1819	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	6566788	0	0
T1	5507	592	0	0
T2	26013	8751	0	0
T3	1861	1266	0	0
T4	2662	1897	0	0
T5	5702	576	0	0
T6	2336	1409	0	0
T7	42310	24676	0	0
T8	2647	2072	0	0
T9	26089	8706	0	0
T10	179080	19649	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	190667	0	0
T2	26013	1135	0	0
T3	1861	0	0	0
T4	2662	118	0	0
T5	5702	0	0	0
T6	2336	49	0	0
T7	42310	1097	0	0
T8	2647	0	0	0
T9	26089	1167	0	0
T10	179080	0	0	0
T11	4536	278	0	0
T12	0	300	0	0
T13	0	525	0	0
T14	0	229	0	0
T15	0	2932	0	0