Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T13,T15
0	1	Covered	T13,T15,T73
1	0	Covered	T13,T15,T73

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T6,T13,T15
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52787087	8577	0	0
CascadeEffAonToRstPorAboveRise_A	52787087	8577	0	0
CascadeEffAonToRstPorIoAboveFall_A	50673719	8577	0	0
CascadeEffAonToRstPorIoAboveRise_A	50673719	8577	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25337611	8577	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25337611	8577	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12668563	8577	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12668563	8577	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25337636	8577	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25337636	8577	0	0
CascadeLcToLcAboveFall_A	52787087	21523	0	0
CascadeLcToLcAboveRise_A	52787087	21523	0	0
CascadeLcToLcAonAboveFall_A	1600013	21523	0	0
CascadeLcToLcAonAboveRise_A	1600013	21523	0	0
CascadeLcToLcShadowedAboveFall_A	52787087	21523	0	0
CascadeLcToLcShadowedAboveRise_A	52787087	21523	0	0
CascadePorToAonAboveFall_A	1600013	6831	0	0
CascadeSysToSysAboveFall_A	52787087	21523	0	0
CascadeSysToSysAboveRise_A	52787087	21523	0	0
ScanRstToAonRise_A	1600013	190	0	0
StablePorToAonRise_A	1600013	8577	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11217590	21523	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11217590	21523	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11217590	21523	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11217590	21523	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12668563	21523	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12668563	21523	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11217590	21523	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11217590	21523	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11217590	21523	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11217590	21523	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	8577	0	0
T1	24420	8	0	0
T2	122408	27	0	0
T3	8036	1	0	0
T4	12880	1	0	0
T5	24436	8	0	0
T6	11119	2	0	0
T7	189041	27	0	0
T8	11411	1	0	0
T9	121697	27	0	0
T10	823373	271	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	8577	0	0
T1	24420	8	0	0
T2	122408	27	0	0
T3	8036	1	0	0
T4	12880	1	0	0
T5	24436	8	0	0
T6	11119	2	0	0
T7	189041	27	0	0
T8	11411	1	0	0
T9	121697	27	0	0
T10	823373	271	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50673719	8577	0	0
T1	23441	8	0	0
T2	117522	27	0	0
T3	7714	1	0	0
T4	12365	1	0	0
T5	23440	8	0	0
T6	10677	2	0	0
T7	181489	27	0	0
T8	10953	1	0	0
T9	116844	27	0	0
T10	790389	271	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50673719	8577	0	0
T1	23441	8	0	0
T2	117522	27	0	0
T3	7714	1	0	0
T4	12365	1	0	0
T5	23440	8	0	0
T6	10677	2	0	0
T7	181489	27	0	0
T8	10953	1	0	0
T9	116844	27	0	0
T10	790389	271	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337611	8577	0	0
T1	11725	8	0	0
T2	58767	27	0	0
T3	3856	1	0	0
T4	6182	1	0	0
T5	11722	8	0	0
T6	5339	2	0	0
T7	90726	27	0	0
T8	5477	1	0	0
T9	58410	27	0	0
T10	395218	271	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337611	8577	0	0
T1	11725	8	0	0
T2	58767	27	0	0
T3	3856	1	0	0
T4	6182	1	0	0
T5	11722	8	0	0
T6	5339	2	0	0
T7	90726	27	0	0
T8	5477	1	0	0
T9	58410	27	0	0
T10	395218	271	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	8577	0	0
T1	5858	8	0	0
T2	29395	27	0	0
T3	1928	1	0	0
T4	3090	1	0	0
T5	5858	8	0	0
T6	2668	2	0	0
T7	45369	27	0	0
T8	2738	1	0	0
T9	29209	27	0	0
T10	197631	271	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	8577	0	0
T1	5858	8	0	0
T2	29395	27	0	0
T3	1928	1	0	0
T4	3090	1	0	0
T5	5858	8	0	0
T6	2668	2	0	0
T7	45369	27	0	0
T8	2738	1	0	0
T9	29209	27	0	0
T10	197631	271	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337636	8577	0	0
T1	11722	8	0	0
T2	58751	27	0	0
T3	3857	1	0	0
T4	6182	1	0	0
T5	11722	8	0	0
T6	5341	2	0	0
T7	90721	27	0	0
T8	5477	1	0	0
T9	58411	27	0	0
T10	395203	271	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337636	8577	0	0
T1	11722	8	0	0
T2	58751	27	0	0
T3	3857	1	0	0
T4	6182	1	0	0
T5	11722	8	0	0
T6	5341	2	0	0
T7	90721	27	0	0
T8	5477	1	0	0
T9	58411	27	0	0
T10	395203	271	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	21523	0	0
T1	24420	8	0	0
T2	122408	102	0	0
T3	8036	1	0	0
T4	12880	9	0	0
T5	24436	8	0	0
T6	11119	6	0	0
T7	189041	102	0	0
T8	11411	1	0	0
T9	121697	102	0	0
T10	823373	271	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	21523	0	0
T1	24420	8	0	0
T2	122408	102	0	0
T3	8036	1	0	0
T4	12880	9	0	0
T5	24436	8	0	0
T6	11119	6	0	0
T7	189041	102	0	0
T8	11411	1	0	0
T9	121697	102	0	0
T10	823373	271	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	21523	0	0
T1	735	8	0	0
T2	3686	102	0	0
T3	240	1	0	0
T4	385	9	0	0
T5	734	8	0	0
T6	333	6	0	0
T7	5685	102	0	0
T8	341	1	0	0
T9	3667	102	0	0
T10	24823	271	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	21523	0	0
T1	735	8	0	0
T2	3686	102	0	0
T3	240	1	0	0
T4	385	9	0	0
T5	734	8	0	0
T6	333	6	0	0
T7	5685	102	0	0
T8	341	1	0	0
T9	3667	102	0	0
T10	24823	271	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	21523	0	0
T1	24420	8	0	0
T2	122408	102	0	0
T3	8036	1	0	0
T4	12880	9	0	0
T5	24436	8	0	0
T6	11119	6	0	0
T7	189041	102	0	0
T8	11411	1	0	0
T9	121697	102	0	0
T10	823373	271	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	21523	0	0
T1	24420	8	0	0
T2	122408	102	0	0
T3	8036	1	0	0
T4	12880	9	0	0
T5	24436	8	0	0
T6	11119	6	0	0
T7	189041	102	0	0
T8	11411	1	0	0
T9	121697	102	0	0
T10	823373	271	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	6831	0	0
T1	735	8	0	0
T2	3686	27	0	0
T3	240	1	0	0
T4	385	1	0	0
T5	734	8	0	0
T6	333	1	0	0
T7	5685	27	0	0
T8	341	1	0	0
T9	3667	27	0	0
T10	24823	271	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	21523	0	0
T1	24420	8	0	0
T2	122408	102	0	0
T3	8036	1	0	0
T4	12880	9	0	0
T5	24436	8	0	0
T6	11119	6	0	0
T7	189041	102	0	0
T8	11411	1	0	0
T9	121697	102	0	0
T10	823373	271	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52787087	21523	0	0
T1	24420	8	0	0
T2	122408	102	0	0
T3	8036	1	0	0
T4	12880	9	0	0
T5	24436	8	0	0
T6	11119	6	0	0
T7	189041	102	0	0
T8	11411	1	0	0
T9	121697	102	0	0
T10	823373	271	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	190	0	0
T15	31309	2	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	0	1	0	0
T44	0	9	0	0
T54	401	0	0	0
T55	748	0	0	0
T60	1442	0	0	0
T72	308	0	0	0
T73	3205	0	0	0
T74	2167	0	0	0
T75	524	0	0	0
T76	519	0	0	0
T77	0	1	0	0
T80	0	3	0	0
T81	0	9	0	0
T91	0	2	0	0
T93	257	0	0	0
T96	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	8577	0	0
T1	735	8	0	0
T2	3686	27	0	0
T3	240	1	0	0
T4	385	1	0	0
T5	734	8	0	0
T6	333	2	0	0
T7	5685	27	0	0
T8	341	1	0	0
T9	3667	27	0	0
T10	24823	271	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	21523	0	0
T1	5858	8	0	0
T2	29395	102	0	0
T3	1928	1	0	0
T4	3090	9	0	0
T5	5858	8	0	0
T6	2668	6	0	0
T7	45369	102	0	0
T8	2738	1	0	0
T9	29209	102	0	0
T10	197631	271	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	21523	0	0
T1	5858	8	0	0
T2	29395	102	0	0
T3	1928	1	0	0
T4	3090	9	0	0
T5	5858	8	0	0
T6	2668	6	0	0
T7	45369	102	0	0
T8	2738	1	0	0
T9	29209	102	0	0
T10	197631	271	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11217590	21523	0	0
T1	5507	8	0	0
T2	26013	102	0	0
T3	1861	1	0	0
T4	2662	9	0	0
T5	5702	8	0	0
T6	2336	6	0	0
T7	42310	102	0	0
T8	2647	1	0	0
T9	26089	102	0	0
T10	179080	271	0	0