Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T14,T15
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T60
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T60
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T60
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T60
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T60
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T15,T60
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12668563	13792	0	0
gen_assertions[0].RstEnOn_A	12668563	1031	0	0
gen_assertions[0].RstNOff_A	12668563	13792	0	0
gen_assertions[0].RstNOn_A	12668563	1031	0	0
gen_assertions[1].RstEnOff_A	50673719	12564	0	0
gen_assertions[1].RstEnOn_A	50673719	962	0	0
gen_assertions[1].RstNOff_A	50673719	12564	0	0
gen_assertions[1].RstNOn_A	50673719	962	0	0
gen_assertions[2].RstEnOff_A	25337611	12621	0	0
gen_assertions[2].RstEnOn_A	25337611	982	0	0
gen_assertions[2].RstNOff_A	25337611	12621	0	0
gen_assertions[2].RstNOn_A	25337611	982	0	0
gen_assertions[3].RstEnOff_A	25337636	12677	0	0
gen_assertions[3].RstEnOn_A	25337636	1037	0	0
gen_assertions[3].RstNOff_A	25337636	12677	0	0
gen_assertions[3].RstNOn_A	25337636	1037	0	0
gen_assertions[4].RstEnOff_A	1600013	21230	0	0
gen_assertions[4].RstEnOn_A	1600013	1074	0	0
gen_assertions[4].RstNOff_A	1600013	21230	0	0
gen_assertions[4].RstNOn_A	1600013	1074	0	0
gen_assertions[5].RstEnOff_A	12668563	14005	0	0
gen_assertions[5].RstEnOn_A	12668563	1100	0	0
gen_assertions[5].RstNOff_A	12668563	14005	0	0
gen_assertions[5].RstNOn_A	12668563	1100	0	0
gen_assertions[6].RstEnOff_A	12668563	14076	0	0
gen_assertions[6].RstEnOn_A	12668563	1175	0	0
gen_assertions[6].RstNOff_A	12668563	14076	0	0
gen_assertions[6].RstNOn_A	12668563	1175	0	0
gen_assertions[7].RstEnOff_A	12668563	14109	0	0
gen_assertions[7].RstEnOn_A	12668563	1207	0	0
gen_assertions[7].RstNOff_A	12668563	14109	0	0
gen_assertions[7].RstNOn_A	12668563	1207	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	13792	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	0	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0
T15	0	231	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1031	0	0
T4	3090	1	0	0
T5	5858	0	0	0
T6	2668	0	0	0
T7	45369	0	0	0
T8	2738	0	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	5	0	0
T12	0	1	0	0
T14	0	10	0	0
T15	0	32	0	0
T53	1703	0	0	0
T54	0	7	0	0
T55	0	4	0	0
T59	1550	0	0	0
T60	0	5	0	0
T61	0	1	0	0
T78	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	13792	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	0	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0
T15	0	231	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1031	0	0
T4	3090	1	0	0
T5	5858	0	0	0
T6	2668	0	0	0
T7	45369	0	0	0
T8	2738	0	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	5	0	0
T12	0	1	0	0
T14	0	10	0	0
T15	0	32	0	0
T53	1703	0	0	0
T54	0	7	0	0
T55	0	4	0	0
T59	1550	0	0	0
T60	0	5	0	0
T61	0	1	0	0
T78	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50673719	12564	0	0
T2	117522	65	0	0
T3	7714	0	0	0
T4	12365	7	0	0
T5	23440	0	0	0
T6	10677	3	0	0
T7	181489	69	0	0
T8	10953	2	0	0
T9	116844	71	0	0
T10	790389	0	0	0
T11	22794	18	0	0
T12	0	18	0	0
T13	0	33	0	0
T14	0	13	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50673719	962	0	0
T8	10953	2	0	0
T9	116844	0	0	0
T10	790389	0	0	0
T11	22794	0	0	0
T12	24118	0	0	0
T13	127389	0	0	0
T14	13356	5	0	0
T15	989626	35	0	0
T28	0	10	0	0
T30	0	7	0	0
T44	0	12	0	0
T53	6818	0	0	0
T54	0	4	0	0
T59	6211	0	0	0
T60	0	5	0	0
T79	0	4	0	0
T80	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50673719	12564	0	0
T2	117522	65	0	0
T3	7714	0	0	0
T4	12365	7	0	0
T5	23440	0	0	0
T6	10677	3	0	0
T7	181489	69	0	0
T8	10953	2	0	0
T9	116844	71	0	0
T10	790389	0	0	0
T11	22794	18	0	0
T12	0	18	0	0
T13	0	33	0	0
T14	0	13	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50673719	962	0	0
T8	10953	2	0	0
T9	116844	0	0	0
T10	790389	0	0	0
T11	22794	0	0	0
T12	24118	0	0	0
T13	127389	0	0	0
T14	13356	5	0	0
T15	989626	35	0	0
T28	0	10	0	0
T30	0	7	0	0
T44	0	12	0	0
T53	6818	0	0	0
T54	0	4	0	0
T59	6211	0	0	0
T60	0	5	0	0
T79	0	4	0	0
T80	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337611	12621	0	0
T2	58767	65	0	0
T3	3856	0	0	0
T4	6182	7	0	0
T5	11722	0	0	0
T6	5339	3	0	0
T7	90726	69	0	0
T8	5477	2	0	0
T9	58410	71	0	0
T10	395218	0	0	0
T11	11398	18	0	0
T12	0	18	0	0
T13	0	33	0	0
T14	0	13	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337611	982	0	0
T8	5477	2	0	0
T9	58410	0	0	0
T10	395218	0	0	0
T11	11398	0	0	0
T12	12059	0	0	0
T13	63694	0	0	0
T14	6677	0	0	0
T15	494813	35	0	0
T28	0	11	0	0
T30	0	9	0	0
T44	0	10	0	0
T53	3409	0	0	0
T54	0	1	0	0
T59	3104	0	0	0
T60	0	6	0	0
T79	0	9	0	0
T80	0	9	0	0
T81	0	42	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337611	12621	0	0
T2	58767	65	0	0
T3	3856	0	0	0
T4	6182	7	0	0
T5	11722	0	0	0
T6	5339	3	0	0
T7	90726	69	0	0
T8	5477	2	0	0
T9	58410	71	0	0
T10	395218	0	0	0
T11	11398	18	0	0
T12	0	18	0	0
T13	0	33	0	0
T14	0	13	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337611	982	0	0
T8	5477	2	0	0
T9	58410	0	0	0
T10	395218	0	0	0
T11	11398	0	0	0
T12	12059	0	0	0
T13	63694	0	0	0
T14	6677	0	0	0
T15	494813	35	0	0
T28	0	11	0	0
T30	0	9	0	0
T44	0	10	0	0
T53	3409	0	0	0
T54	0	1	0	0
T59	3104	0	0	0
T60	0	6	0	0
T79	0	9	0	0
T80	0	9	0	0
T81	0	42	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337636	12677	0	0
T2	58751	65	0	0
T3	3857	0	0	0
T4	6182	7	0	0
T5	11722	0	0	0
T6	5341	3	0	0
T7	90721	69	0	0
T8	5477	4	0	0
T9	58411	71	0	0
T10	395203	0	0	0
T11	11398	18	0	0
T12	0	18	0	0
T13	0	33	0	0
T14	0	13	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337636	1037	0	0
T8	5477	4	0	0
T9	58411	0	0	0
T10	395203	0	0	0
T11	11398	0	0	0
T12	12059	0	0	0
T13	63705	0	0	0
T14	6677	0	0	0
T15	494815	34	0	0
T28	0	12	0	0
T30	0	8	0	0
T44	0	11	0	0
T53	3408	0	0	0
T59	3104	0	0	0
T60	0	9	0	0
T61	0	1	0	0
T79	0	7	0	0
T80	0	10	0	0
T81	0	47	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337636	12677	0	0
T2	58751	65	0	0
T3	3857	0	0	0
T4	6182	7	0	0
T5	11722	0	0	0
T6	5341	3	0	0
T7	90721	69	0	0
T8	5477	4	0	0
T9	58411	71	0	0
T10	395203	0	0	0
T11	11398	18	0	0
T12	0	18	0	0
T13	0	33	0	0
T14	0	13	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25337636	1037	0	0
T8	5477	4	0	0
T9	58411	0	0	0
T10	395203	0	0	0
T11	11398	0	0	0
T12	12059	0	0	0
T13	63705	0	0	0
T14	6677	0	0	0
T15	494815	34	0	0
T28	0	12	0	0
T30	0	8	0	0
T44	0	11	0	0
T53	3408	0	0	0
T59	3104	0	0	0
T60	0	9	0	0
T61	0	1	0	0
T79	0	7	0	0
T80	0	10	0	0
T81	0	47	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	21230	0	0
T1	735	3	0	0
T2	3686	75	0	0
T3	240	1	0	0
T4	385	9	0	0
T5	734	3	0	0
T6	333	5	0	0
T7	5685	91	0	0
T8	341	6	0	0
T9	3667	75	0	0
T10	24823	271	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	1074	0	0
T8	341	5	0	0
T9	3667	0	0	0
T10	24823	0	0	0
T11	710	0	0	0
T12	752	0	0	0
T13	4065	0	0	0
T14	416	0	0	0
T15	31309	29	0	0
T28	0	7	0	0
T30	0	11	0	0
T44	0	10	0	0
T53	212	0	0	0
T59	193	0	0	0
T60	0	9	0	0
T79	0	9	0	0
T80	0	9	0	0
T81	0	50	0	0
T82	0	15	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	21230	0	0
T1	735	3	0	0
T2	3686	75	0	0
T3	240	1	0	0
T4	385	9	0	0
T5	734	3	0	0
T6	333	5	0	0
T7	5685	91	0	0
T8	341	6	0	0
T9	3667	75	0	0
T10	24823	271	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1600013	1074	0	0
T8	341	5	0	0
T9	3667	0	0	0
T10	24823	0	0	0
T11	710	0	0	0
T12	752	0	0	0
T13	4065	0	0	0
T14	416	0	0	0
T15	31309	29	0	0
T28	0	7	0	0
T30	0	11	0	0
T44	0	10	0	0
T53	212	0	0	0
T59	193	0	0	0
T60	0	9	0	0
T79	0	9	0	0
T80	0	9	0	0
T81	0	50	0	0
T82	0	15	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	14005	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	6	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1100	0	0
T8	2738	6	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	0	0	0
T12	6029	0	0	0
T13	31855	0	0	0
T14	3338	0	0	0
T15	247413	26	0	0
T28	0	7	0	0
T30	0	11	0	0
T44	0	10	0	0
T53	1703	0	0	0
T59	1550	0	0	0
T60	0	11	0	0
T79	0	9	0	0
T80	0	6	0	0
T81	0	49	0	0
T82	0	11	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	14005	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	6	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1100	0	0
T8	2738	6	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	0	0	0
T12	6029	0	0	0
T13	31855	0	0	0
T14	3338	0	0	0
T15	247413	26	0	0
T28	0	7	0	0
T30	0	11	0	0
T44	0	10	0	0
T53	1703	0	0	0
T59	1550	0	0	0
T60	0	11	0	0
T79	0	9	0	0
T80	0	6	0	0
T81	0	49	0	0
T82	0	11	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	14076	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	7	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1175	0	0
T8	2738	7	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	0	0	0
T12	6029	0	0	0
T13	31855	0	0	0
T14	3338	0	0	0
T15	247413	31	0	0
T28	0	11	0	0
T30	0	11	0	0
T44	0	11	0	0
T53	1703	0	0	0
T59	1550	0	0	0
T60	0	11	0	0
T79	0	11	0	0
T80	0	10	0	0
T81	0	45	0	0
T82	0	14	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	14076	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	7	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1175	0	0
T8	2738	7	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	0	0	0
T12	6029	0	0	0
T13	31855	0	0	0
T14	3338	0	0	0
T15	247413	31	0	0
T28	0	11	0	0
T30	0	11	0	0
T44	0	11	0	0
T53	1703	0	0	0
T59	1550	0	0	0
T60	0	11	0	0
T79	0	11	0	0
T80	0	10	0	0
T81	0	45	0	0
T82	0	14	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	14109	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	8	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1207	0	0
T8	2738	8	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	0	0	0
T12	6029	0	0	0
T13	31855	0	0	0
T14	3338	0	0	0
T15	247413	30	0	0
T28	0	9	0	0
T30	0	13	0	0
T44	0	11	0	0
T53	1703	0	0	0
T59	1550	0	0	0
T60	0	13	0	0
T79	0	9	0	0
T80	0	6	0	0
T81	0	45	0	0
T82	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	14109	0	0
T2	29395	75	0	0
T3	1928	0	0	0
T4	3090	8	0	0
T5	5858	0	0	0
T6	2668	4	0	0
T7	45369	75	0	0
T8	2738	8	0	0
T9	29209	75	0	0
T10	197631	0	0	0
T11	5697	19	0	0
T12	0	20	0	0
T13	0	36	0	0
T14	0	15	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12668563	1207	0	0
T8	2738	8	0	0
T9	29209	0	0	0
T10	197631	0	0	0
T11	5697	0	0	0
T12	6029	0	0	0
T13	31855	0	0	0
T14	3338	0	0	0
T15	247413	30	0	0
T28	0	9	0	0
T30	0	13	0	0
T44	0	11	0	0
T53	1703	0	0	0
T59	1550	0	0	0
T60	0	13	0	0
T79	0	9	0	0
T80	0	6	0	0
T81	0	45	0	0
T82	0	10	0	0