Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12089445	8638	0	0
alert_regwen_rd_A	12089445	4893	0	0
cpu_regwen_rd_A	12089445	4886	0	0
sw_rst_ctrl_n_0_rd_A	12089445	7995	0	0
sw_rst_ctrl_n_1_rd_A	12089445	8190	0	0
sw_rst_ctrl_n_2_rd_A	12089445	8217	0	0
sw_rst_ctrl_n_3_rd_A	12089445	7868	0	0
sw_rst_ctrl_n_4_rd_A	12089445	7994	0	0
sw_rst_ctrl_n_5_rd_A	12089445	8305	0	0
sw_rst_ctrl_n_6_rd_A	12089445	8064	0	0
sw_rst_ctrl_n_7_rd_A	12089445	8307	0	0
sw_rst_regwen_0_rd_A	12089445	5596	0	0
sw_rst_regwen_1_rd_A	12089445	5468	0	0
sw_rst_regwen_2_rd_A	12089445	5496	0	0
sw_rst_regwen_3_rd_A	12089445	5623	0	0
sw_rst_regwen_4_rd_A	12089445	5463	0	0
sw_rst_regwen_5_rd_A	12089445	5632	0	0
sw_rst_regwen_6_rd_A	12089445	5266	0	0
sw_rst_regwen_7_rd_A	12089445	5205	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	8638	0	0
T63	4022	250	0	0
T65	25357	2	0	0
T66	7011	284	0	0
T67	10211	519	0	0
T69	3685	154	0	0
T84	11020	2	0	0
T85	3044	23	0	0
T86	21921	3	0	0
T87	4205	210	0	0
T115	18968	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	4893	0	0
T15	220697	169	0	0
T27	0	74	0	0
T28	0	44	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	0	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	43	0	0
T93	2045	0	0	0
T94	0	38	0	0
T96	0	62	0	0
T116	0	88	0	0
T117	0	42	0	0
T118	0	279	0	0
T119	0	28	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	4886	0	0
T15	220697	189	0	0
T27	0	58	0	0
T28	0	55	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	0	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	59	0	0
T93	2045	0	0	0
T94	0	51	0	0
T96	0	68	0	0
T116	0	81	0	0
T117	0	35	0	0
T118	0	312	0	0
T119	0	28	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	7995	0	0
T15	220697	439	0	0
T27	0	74	0	0
T28	0	181	0	0
T46	0	18	0	0
T54	2361	0	0	0
T55	5207	51	0	0
T60	11465	187	0	0
T61	0	18	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	140	0	0
T93	2045	0	0	0
T94	0	44	0	0
T96	0	50	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	8190	0	0
T15	220697	450	0	0
T27	0	70	0	0
T28	0	211	0	0
T46	0	30	0	0
T54	2361	0	0	0
T55	5207	44	0	0
T60	11465	174	0	0
T61	0	16	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	174	0	0
T93	2045	0	0	0
T94	0	61	0	0
T96	0	63	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	8217	0	0
T15	220697	531	0	0
T27	0	81	0	0
T28	0	192	0	0
T46	0	50	0	0
T54	2361	0	0	0
T55	5207	69	0	0
T60	11465	179	0	0
T61	0	15	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	189	0	0
T93	2045	0	0	0
T94	0	37	0	0
T96	0	62	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	7868	0	0
T15	220697	382	0	0
T27	0	73	0	0
T28	0	185	0	0
T46	0	39	0	0
T54	2361	0	0	0
T55	5207	56	0	0
T60	11465	191	0	0
T61	0	13	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	163	0	0
T93	2045	0	0	0
T94	0	53	0	0
T96	0	50	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	7994	0	0
T15	220697	415	0	0
T27	0	72	0	0
T28	0	179	0	0
T46	0	18	0	0
T54	2361	0	0	0
T55	5207	48	0	0
T60	11465	171	0	0
T61	0	14	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	112	0	0
T93	2045	0	0	0
T94	0	69	0	0
T96	0	66	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	8305	0	0
T15	220697	551	0	0
T27	0	52	0	0
T28	0	177	0	0
T46	0	28	0	0
T54	2361	0	0	0
T55	5207	49	0	0
T60	11465	182	0	0
T61	0	13	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	115	0	0
T93	2045	0	0	0
T94	0	64	0	0
T96	0	76	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	8064	0	0
T15	220697	426	0	0
T27	0	74	0	0
T28	0	179	0	0
T46	0	30	0	0
T54	2361	0	0	0
T55	5207	48	0	0
T60	11465	188	0	0
T61	0	15	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	201	0	0
T93	2045	0	0	0
T94	0	31	0	0
T96	0	58	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	8307	0	0
T15	220697	539	0	0
T27	0	67	0	0
T28	0	181	0	0
T46	0	25	0	0
T54	2361	0	0	0
T55	5207	59	0	0
T60	11465	216	0	0
T61	0	9	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	171	0	0
T93	2045	0	0	0
T94	0	66	0	0
T96	0	61	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5596	0	0
T15	220697	162	0	0
T27	0	71	0	0
T28	0	64	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	33	0	0
T61	0	8	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	38	0	0
T93	2045	0	0	0
T94	0	64	0	0
T96	0	71	0	0
T116	0	57	0	0
T120	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5468	0	0
T15	220697	207	0	0
T27	0	75	0	0
T28	0	53	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	26	0	0
T61	0	5	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	64	0	0
T93	2045	0	0	0
T94	0	30	0	0
T96	0	64	0	0
T116	0	75	0	0
T121	0	30	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5496	0	0
T15	220697	156	0	0
T27	0	78	0	0
T28	0	78	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	29	0	0
T61	0	4	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	34	0	0
T93	2045	0	0	0
T94	0	44	0	0
T96	0	56	0	0
T116	0	60	0	0
T120	0	4	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5623	0	0
T15	220697	153	0	0
T27	0	70	0	0
T28	0	55	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	32	0	0
T61	0	11	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	43	0	0
T93	2045	0	0	0
T94	0	58	0	0
T96	0	61	0	0
T116	0	82	0	0
T120	0	5	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5463	0	0
T15	220697	185	0	0
T27	0	62	0	0
T28	0	77	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	29	0	0
T61	0	2	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	68	0	0
T93	2045	0	0	0
T94	0	41	0	0
T96	0	58	0	0
T116	0	81	0	0
T120	0	6	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5632	0	0
T15	220697	231	0	0
T27	0	60	0	0
T28	0	47	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	34	0	0
T61	0	12	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	24	0	0
T93	2045	0	0	0
T94	0	34	0	0
T96	0	67	0	0
T116	0	90	0	0
T120	0	2	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5266	0	0
T15	220697	213	0	0
T27	0	63	0	0
T28	0	66	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	29	0	0
T61	0	9	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	46	0	0
T93	2045	0	0	0
T94	0	48	0	0
T96	0	49	0	0
T116	0	79	0	0
T120	0	1	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12089445	5205	0	0
T15	220697	154	0	0
T27	0	61	0	0
T28	0	81	0	0
T54	2361	0	0	0
T55	5207	0	0	0
T60	11465	29	0	0
T61	0	6	0	0
T72	2086	0	0	0
T73	20031	0	0	0
T74	12348	0	0	0
T75	4058	0	0	0
T76	3880	0	0	0
T82	0	24	0	0
T93	2045	0	0	0
T94	0	51	0	0
T96	0	48	0	0
T116	0	82	0	0
T120	0	8	0	0