RSTMGR Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rstmgr_smoke 1.580s 235.246us 50 50 100.00
V1 csr_hw_reset rstmgr_csr_hw_reset 1.000s 143.202us 5 5 100.00
V1 csr_rw rstmgr_csr_rw 0.920s 74.324us 20 20 100.00
V1 csr_bit_bash rstmgr_csr_bit_bash 9.690s 2.283ms 5 5 100.00
V1 csr_aliasing rstmgr_csr_aliasing 2.520s 357.953us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rstmgr_csr_mem_rw_with_rand_reset 2.140s 199.781us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rstmgr_csr_rw 0.920s 74.324us 20 20 100.00
rstmgr_csr_aliasing 2.520s 357.953us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 reset_stretcher rstmgr_por_stretcher 1.050s 219.661us 50 50 100.00
V2 sw_rst rstmgr_sw_rst 2.760s 481.752us 50 50 100.00
V2 sw_rst_reset_race rstmgr_sw_rst_reset_race 1.580s 251.453us 50 50 100.00
V2 reset_info rstmgr_reset 7.770s 2.011ms 50 50 100.00
V2 cpu_info rstmgr_reset 7.770s 2.011ms 50 50 100.00
V2 alert_info rstmgr_reset 7.770s 2.011ms 50 50 100.00
V2 reset_info_capture rstmgr_reset 7.770s 2.011ms 50 50 100.00
V2 stress_all rstmgr_stress_all 57.400s 14.677ms 50 50 100.00
V2 alert_test rstmgr_alert_test 1.150s 251.948us 50 50 100.00
V2 tl_d_oob_addr_access rstmgr_tl_errors 3.380s 435.497us 20 20 100.00
V2 tl_d_illegal_access rstmgr_tl_errors 3.380s 435.497us 20 20 100.00
V2 tl_d_outstanding_access rstmgr_csr_hw_reset 1.000s 143.202us 5 5 100.00
rstmgr_csr_rw 0.920s 74.324us 20 20 100.00
rstmgr_csr_aliasing 2.520s 357.953us 5 5 100.00
rstmgr_same_csr_outstanding 1.630s 282.414us 20 20 100.00
V2 tl_d_partial_access rstmgr_csr_hw_reset 1.000s 143.202us 5 5 100.00
rstmgr_csr_rw 0.920s 74.324us 20 20 100.00
rstmgr_csr_aliasing 2.520s 357.953us 5 5 100.00
rstmgr_same_csr_outstanding 1.630s 282.414us 20 20 100.00
V2 TOTAL 340 340 100.00
V2S tl_intg_err rstmgr_sec_cm 26.940s 18.181ms 5 5 100.00
rstmgr_tl_intg_err 3.560s 946.124us 20 20 100.00
V2S prim_count_check rstmgr_sec_cm 26.940s 18.181ms 5 5 100.00
V2S prim_fsm_check rstmgr_sec_cm 26.940s 18.181ms 5 5 100.00
V2S sec_cm_bus_integrity rstmgr_tl_intg_err 3.560s 946.124us 20 20 100.00
V2S sec_cm_scan_intersig_mubi rstmgr_sec_cm_scan_intersig_mubi 1.280s 175.447us 50 50 100.00
V2S sec_cm_leaf_rst_bkgn_chk rstmgr_leaf_rst_cnsty 8.820s 2.350ms 49 50 98.00
V2S sec_cm_leaf_rst_shadow rstmgr_leaf_rst_shadow_attack 1.210s 244.525us 50 50 100.00
V2S sec_cm_leaf_fsm_sparse rstmgr_sec_cm 26.940s 18.181ms 5 5 100.00
V2S sec_cm_sw_rst_config_regwen rstmgr_csr_rw 0.920s 74.324us 20 20 100.00
V2S sec_cm_dump_ctrl_config_regwen rstmgr_csr_rw 0.920s 74.324us 20 20 100.00
V2S TOTAL 174 175 99.43
V3 stress_all_with_rand_reset rstmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 619 620 99.84

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 8 8 8 100.00
V2S 5 5 4 80.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.44 99.40 99.31 99.87 -- 99.83 99.46 98.77

Failure Buckets

Past Results