Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	627390	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

375531

1

T1

125

T2

1062

T3

140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	534929	1			T1	186		T2	1563		T3	186
values[0x0]	233624	1			T1	101		T2	661		T3	90
values[0x1]	234368	1			T1	92		T2	681		T3	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	526873	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

476048

1

T1

168

T2

1334

T3

178

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3631	1			T1	1		T2	12		T3	5
valid_sources[0x01]	3407	1			T1	2		T2	16		T9	12
valid_sources[0x02]	3393	1			T2	11		T9	11		T21	13
valid_sources[0x03]	3688	1			T1	1		T2	27		T9	16
valid_sources[0x04]	4150	1			T1	3		T2	14		T3	5
valid_sources[0x05]	3476	1			T1	2		T2	11		T3	1
valid_sources[0x06]	4252	1			T1	2		T2	12		T9	15
valid_sources[0x07]	3442	1			T2	19		T3	3		T9	10
valid_sources[0x08]	4436	1			T1	1		T2	7		T3	1
valid_sources[0x09]	3704	1			T1	5		T2	14		T3	2
valid_sources[0x0a]	3616	1			T2	11		T9	15		T51	58
valid_sources[0x0b]	3348	1			T1	4		T2	13		T3	1
valid_sources[0x0c]	3236	1			T1	1		T2	3		T9	10
valid_sources[0x0d]	3611	1			T1	3		T2	16		T3	1
valid_sources[0x0e]	3608	1			T1	1		T2	17		T3	1
valid_sources[0x0f]	3904	1			T1	2		T2	4		T3	1
valid_sources[0x10]	4868	1			T1	2		T2	14		T3	2
valid_sources[0x11]	3235	1			T2	12		T9	19		T12	1
valid_sources[0x12]	3562	1			T1	1		T2	14		T3	2
valid_sources[0x13]	3624	1			T2	9		T9	13		T12	15
valid_sources[0x14]	3947	1			T1	3		T2	8		T9	6
valid_sources[0x15]	3327	1			T2	7		T3	1		T9	10
valid_sources[0x16]	5192	1			T1	1		T2	15		T9	27
valid_sources[0x17]	5077	1			T1	4		T2	16		T8	1
valid_sources[0x18]	3868	1			T1	4		T2	2		T3	4
valid_sources[0x19]	3683	1			T2	15		T9	15		T51	42
valid_sources[0x1a]	4087	1			T1	1		T2	3		T3	1
valid_sources[0x1b]	3744	1			T1	3		T2	11		T9	9
valid_sources[0x1c]	3654	1			T2	13		T9	10		T12	2
valid_sources[0x1d]	4391	1			T1	2		T2	13		T3	1
valid_sources[0x1e]	4788	1			T2	11		T3	4		T9	11
valid_sources[0x1f]	3696	1			T1	2		T2	8		T3	5
valid_sources[0x20]	3218	1			T2	13		T3	3		T9	10
valid_sources[0x21]	3658	1			T1	1		T2	9		T3	2
valid_sources[0x22]	3992	1			T1	2		T2	11		T3	1
valid_sources[0x23]	4602	1			T2	19		T3	3		T9	9
valid_sources[0x24]	6766	1			T1	6		T2	14		T3	1
valid_sources[0x25]	3834	1			T1	2		T2	7		T3	6
valid_sources[0x26]	3747	1			T1	1		T2	10		T3	5
valid_sources[0x27]	3639	1			T1	3		T2	3		T9	11
valid_sources[0x28]	4706	1			T1	2		T2	6		T3	3
valid_sources[0x29]	6987	1			T2	12		T9	13		T12	1
valid_sources[0x2a]	3839	1			T2	16		T9	10		T12	2
valid_sources[0x2b]	3639	1			T1	1		T2	7		T9	10
valid_sources[0x2c]	3860	1			T1	2		T2	8		T3	1
valid_sources[0x2d]	3649	1			T2	24		T3	2		T9	16
valid_sources[0x2e]	3511	1			T2	15		T9	13		T51	50
valid_sources[0x2f]	4486	1			T1	1		T2	15		T9	24
valid_sources[0x30]	7440	1			T1	2		T2	15		T9	8
valid_sources[0x31]	4406	1			T1	1		T2	34		T3	2
valid_sources[0x32]	3629	1			T1	1		T2	5		T9	12
valid_sources[0x33]	4914	1			T1	1		T2	2		T3	1
valid_sources[0x34]	3585	1			T1	2		T2	18		T3	2
valid_sources[0x35]	7541	1			T1	3		T2	29		T3	5
valid_sources[0x36]	4174	1			T2	3		T9	15		T51	40
valid_sources[0x37]	3637	1			T1	3		T2	11		T3	3
valid_sources[0x38]	3934	1			T2	11		T9	16		T12	4
valid_sources[0x39]	5272	1			T1	1		T2	10		T3	3
valid_sources[0x3a]	3606	1			T2	8		T3	3		T9	11
valid_sources[0x3b]	3414	1			T1	1		T2	1		T9	7
valid_sources[0x3c]	4896	1			T2	18		T9	11		T51	64
valid_sources[0x3d]	4118	1			T1	2		T2	8		T3	1
valid_sources[0x3e]	3566	1			T1	1		T2	8		T9	21
valid_sources[0x3f]	4107	1			T1	2		T2	14		T9	9
valid_sources[0x40]	4034	1			T1	4		T2	18		T3	2
valid_sources[0x41]	3639	1			T1	1		T2	19		T9	11
valid_sources[0x42]	3646	1			T1	1		T2	11		T9	17
valid_sources[0x43]	3903	1			T2	9		T9	11		T51	36
valid_sources[0x44]	3531	1			T1	2		T3	1		T9	17
valid_sources[0x45]	3893	1			T1	3		T2	22		T3	2
valid_sources[0x46]	4000	1			T1	2		T2	6		T3	2
valid_sources[0x47]	4655	1			T1	3		T2	17		T9	11
valid_sources[0x48]	3449	1			T1	4		T2	4		T3	5
valid_sources[0x49]	3530	1			T1	3		T2	13		T3	2
valid_sources[0x4a]	3534	1			T2	11		T9	16		T51	77
valid_sources[0x4b]	3586	1			T1	1		T2	16		T9	9
valid_sources[0x4c]	4174	1			T1	3		T2	23		T3	2
valid_sources[0x4d]	5105	1			T1	1		T2	4		T3	2
valid_sources[0x4e]	3260	1			T1	2		T2	11		T3	1
valid_sources[0x4f]	4282	1			T1	1		T2	3		T3	4
valid_sources[0x50]	3923	1			T1	2		T3	1		T9	5
valid_sources[0x51]	3799	1			T1	1		T2	10		T3	2
valid_sources[0x52]	3564	1			T1	2		T2	13		T9	11
valid_sources[0x53]	3690	1			T1	1		T2	15		T3	6
valid_sources[0x54]	3657	1			T1	1		T2	11		T9	13
valid_sources[0x55]	3417	1			T2	3		T3	1		T9	18
valid_sources[0x56]	4166	1			T1	1		T2	13		T3	7
valid_sources[0x57]	4566	1			T2	16		T3	1		T9	10
valid_sources[0x58]	3269	1			T1	1		T2	14		T9	13
valid_sources[0x59]	3277	1			T1	2		T2	8		T3	2
valid_sources[0x5a]	4047	1			T1	1		T2	5		T9	4
valid_sources[0x5b]	3334	1			T1	1		T2	3		T3	3
valid_sources[0x5c]	3829	1			T1	1		T2	6		T3	1
valid_sources[0x5d]	3575	1			T1	2		T2	10		T3	2
valid_sources[0x5e]	3340	1			T1	2		T2	7		T3	3
valid_sources[0x5f]	3573	1			T1	2		T2	8		T3	3
valid_sources[0x60]	3482	1			T1	1		T2	7		T3	3
valid_sources[0x61]	3358	1			T1	1		T2	16		T3	2
valid_sources[0x62]	7034	1			T1	1		T2	11		T9	17
valid_sources[0x63]	4214	1			T2	9		T9	20		T12	2
valid_sources[0x64]	3752	1			T2	5		T9	12		T12	1
valid_sources[0x65]	3503	1			T1	1		T2	12		T9	11
valid_sources[0x66]	3286	1			T1	1		T2	17		T3	5
valid_sources[0x67]	3793	1			T1	1		T2	18		T3	1
valid_sources[0x68]	3407	1			T1	1		T2	19		T3	4
valid_sources[0x69]	3804	1			T1	2		T2	12		T3	5
valid_sources[0x6a]	4917	1			T1	1		T2	6		T9	7
valid_sources[0x6b]	3692	1			T1	1		T2	10		T3	1
valid_sources[0x6c]	3804	1			T1	1		T2	11		T9	15
valid_sources[0x6d]	3589	1			T1	1		T2	15		T9	9
valid_sources[0x6e]	3711	1			T1	2		T2	12		T9	15
valid_sources[0x6f]	3914	1			T1	1		T2	3		T3	6
valid_sources[0x70]	3957	1			T2	21		T9	15		T12	6
valid_sources[0x71]	3151	1			T1	1		T2	26		T3	3
valid_sources[0x72]	3404	1			T1	1		T2	5		T9	6
valid_sources[0x73]	3516	1			T1	1		T2	11		T9	9
valid_sources[0x74]	3367	1			T1	1		T2	10		T9	12
valid_sources[0x75]	3946	1			T2	10		T3	2		T9	18
valid_sources[0x76]	3126	1			T1	2		T2	12		T3	1
valid_sources[0x77]	3879	1			T2	23		T9	12		T51	63
valid_sources[0x78]	3484	1			T1	3		T2	14		T3	1
valid_sources[0x79]	3143	1			T1	1		T2	14		T9	15
valid_sources[0x7a]	3493	1			T1	2		T2	13		T3	1
valid_sources[0x7b]	4761	1			T1	1		T2	15		T9	20
valid_sources[0x7c]	3799	1			T2	6		T3	2		T9	10
valid_sources[0x7d]	4764	1			T2	15		T3	6		T9	19
valid_sources[0x7e]	3595	1			T1	4		T2	15		T3	5
valid_sources[0x7f]	3751	1			T1	1		T2	13		T3	3
valid_sources[0x80]	3449	1			T1	1		T2	19		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

250690

1

T1

74

T2

730

T3

90

values[0x0]

all_enables

biggest_size

81307

1

T1

37

T2

209

T3

32

values[0x1]

all_enables

biggest_size

43534

1

T1

14

T2

123

T3

18