Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T12
1	0	Covered	T2,T3,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57118849	8955	0	0
CascadeEffAonToRstPorAboveRise_A	57118849	8955	0	0
CascadeEffAonToRstPorIoAboveFall_A	54832598	8955	0	0
CascadeEffAonToRstPorIoAboveRise_A	54832598	8955	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27417545	8955	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27417545	8955	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13708244	8955	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13708244	8955	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27417270	8955	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27417270	8955	0	0
CascadeLcToLcAboveFall_A	57118849	22332	0	0
CascadeLcToLcAboveRise_A	57118849	22332	0	0
CascadeLcToLcAonAboveFall_A	1730935	22332	0	0
CascadeLcToLcAonAboveRise_A	1730935	22332	0	0
CascadeLcToLcShadowedAboveFall_A	57118849	22332	0	0
CascadeLcToLcShadowedAboveRise_A	57118849	22332	0	0
CascadePorToAonAboveFall_A	1730935	7168	0	0
CascadeSysToSysAboveFall_A	57118849	22332	0	0
CascadeSysToSysAboveRise_A	57118849	22332	0	0
ScanRstToAonRise_A	1730935	220	0	0
StablePorToAonRise_A	1730935	8955	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12170219	22332	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12170219	22332	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12170219	22332	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12170219	22332	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13708244	22332	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13708244	22332	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12170219	22332	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12170219	22332	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12170219	22332	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12170219	22332	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	8955	0	0
T1	12005	2	0	0
T2	147400	15	0	0
T3	12307	2	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	1	0	0
T7	20616	1	0	0
T8	5259	1	0	0
T9	188949	27	0	0
T10	24950	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	8955	0	0
T1	12005	2	0	0
T2	147400	15	0	0
T3	12307	2	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	1	0	0
T7	20616	1	0	0
T8	5259	1	0	0
T9	188949	27	0	0
T10	24950	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54832598	8955	0	0
T1	11522	2	0	0
T2	141502	15	0	0
T3	11815	2	0	0
T4	18189	2	0	0
T5	23289	8	0	0
T6	8852	1	0	0
T7	19790	1	0	0
T8	5050	1	0	0
T9	181389	27	0	0
T10	23947	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54832598	8955	0	0
T1	11522	2	0	0
T2	141502	15	0	0
T3	11815	2	0	0
T4	18189	2	0	0
T5	23289	8	0	0
T6	8852	1	0	0
T7	19790	1	0	0
T8	5050	1	0	0
T9	181389	27	0	0
T10	23947	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417545	8955	0	0
T1	5764	2	0	0
T2	70758	15	0	0
T3	5905	2	0	0
T4	9095	2	0	0
T5	11649	8	0	0
T6	4426	1	0	0
T7	9894	1	0	0
T8	2524	1	0	0
T9	90692	27	0	0
T10	11974	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417545	8955	0	0
T1	5764	2	0	0
T2	70758	15	0	0
T3	5905	2	0	0
T4	9095	2	0	0
T5	11649	8	0	0
T6	4426	1	0	0
T7	9894	1	0	0
T8	2524	1	0	0
T9	90692	27	0	0
T10	11974	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	8955	0	0
T1	2881	2	0	0
T2	35376	15	0	0
T3	2954	2	0	0
T4	4547	2	0	0
T5	5826	8	0	0
T6	2211	1	0	0
T7	4946	1	0	0
T8	1262	1	0	0
T9	45350	27	0	0
T10	5987	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	8955	0	0
T1	2881	2	0	0
T2	35376	15	0	0
T3	2954	2	0	0
T4	4547	2	0	0
T5	5826	8	0	0
T6	2211	1	0	0
T7	4946	1	0	0
T8	1262	1	0	0
T9	45350	27	0	0
T10	5987	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417270	8955	0	0
T1	5763	2	0	0
T2	70748	15	0	0
T3	5902	2	0	0
T4	9095	2	0	0
T5	11647	8	0	0
T6	4426	1	0	0
T7	9894	1	0	0
T8	2523	1	0	0
T9	90707	27	0	0
T10	11973	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417270	8955	0	0
T1	5763	2	0	0
T2	70748	15	0	0
T3	5902	2	0	0
T4	9095	2	0	0
T5	11647	8	0	0
T6	4426	1	0	0
T7	9894	1	0	0
T8	2523	1	0	0
T9	90707	27	0	0
T10	11973	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	22332	0	0
T1	12005	6	0	0
T2	147400	60	0	0
T3	12307	6	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	7	0	0
T7	20616	18	0	0
T8	5259	1	0	0
T9	188949	102	0	0
T10	24950	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	22332	0	0
T1	12005	6	0	0
T2	147400	60	0	0
T3	12307	6	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	7	0	0
T7	20616	18	0	0
T8	5259	1	0	0
T9	188949	102	0	0
T10	24950	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	22332	0	0
T1	360	6	0	0
T2	4502	60	0	0
T3	368	6	0	0
T4	566	2	0	0
T5	730	8	0	0
T6	275	7	0	0
T7	617	18	0	0
T8	157	1	0	0
T9	5682	102	0	0
T10	748	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	22332	0	0
T1	360	6	0	0
T2	4502	60	0	0
T3	368	6	0	0
T4	566	2	0	0
T5	730	8	0	0
T6	275	7	0	0
T7	617	18	0	0
T8	157	1	0	0
T9	5682	102	0	0
T10	748	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	22332	0	0
T1	12005	6	0	0
T2	147400	60	0	0
T3	12307	6	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	7	0	0
T7	20616	18	0	0
T8	5259	1	0	0
T9	188949	102	0	0
T10	24950	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	22332	0	0
T1	12005	6	0	0
T2	147400	60	0	0
T3	12307	6	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	7	0	0
T7	20616	18	0	0
T8	5259	1	0	0
T9	188949	102	0	0
T10	24950	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	7168	0	0
T1	360	1	0	0
T2	4502	10	0	0
T3	368	1	0	0
T4	566	15	0	0
T5	730	8	0	0
T6	275	1	0	0
T7	617	1	0	0
T8	157	1	0	0
T9	5682	27	0	0
T10	748	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	22332	0	0
T1	12005	6	0	0
T2	147400	60	0	0
T3	12307	6	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	7	0	0
T7	20616	18	0	0
T8	5259	1	0	0
T9	188949	102	0	0
T10	24950	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57118849	22332	0	0
T1	12005	6	0	0
T2	147400	60	0	0
T3	12307	6	0	0
T4	18948	2	0	0
T5	24280	8	0	0
T6	9221	7	0	0
T7	20616	18	0	0
T8	5259	1	0	0
T9	188949	102	0	0
T10	24950	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	220	0	0
T2	4502	1	0	0
T3	368	0	0	0
T4	566	0	0	0
T5	730	0	0	0
T6	275	0	0	0
T7	617	0	0	0
T8	157	0	0	0
T9	5682	0	0	0
T10	748	0	0	0
T21	202	0	0	0
T46	0	1	0	0
T50	0	5	0	0
T51	0	3	0	0
T53	0	7	0	0
T62	0	3	0	0
T76	0	6	0	0
T77	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	8955	0	0
T1	360	2	0	0
T2	4502	15	0	0
T3	368	2	0	0
T4	566	2	0	0
T5	730	8	0	0
T6	275	1	0	0
T7	617	1	0	0
T8	157	1	0	0
T9	5682	27	0	0
T10	748	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	22332	0	0
T1	2881	6	0	0
T2	35376	60	0	0
T3	2954	6	0	0
T4	4547	2	0	0
T5	5826	8	0	0
T6	2211	7	0	0
T7	4946	18	0	0
T8	1262	1	0	0
T9	45350	102	0	0
T10	5987	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	22332	0	0
T1	2881	6	0	0
T2	35376	60	0	0
T3	2954	6	0	0
T4	4547	2	0	0
T5	5826	8	0	0
T6	2211	7	0	0
T7	4946	18	0	0
T8	1262	1	0	0
T9	45350	102	0	0
T10	5987	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12170219	22332	0	0
T1	2643	6	0	0
T2	30155	60	0	0
T3	2712	6	0	0
T4	4408	2	0	0
T5	5664	8	0	0
T6	1801	7	0	0
T7	3909	18	0	0
T8	1243	1	0	0
T9	42021	102	0	0
T10	5888	6	0	0