Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T51,T53
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T51,T53
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T51,T53
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T45
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T45
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T45
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13708244	14336	0	0
gen_assertions[0].RstEnOn_A	13708244	1148	0	0
gen_assertions[0].RstNOff_A	13708244	14336	0	0
gen_assertions[0].RstNOn_A	13708244	1148	0	0
gen_assertions[1].RstEnOff_A	54832598	12994	0	0
gen_assertions[1].RstEnOn_A	54832598	1085	0	0
gen_assertions[1].RstNOff_A	54832598	12994	0	0
gen_assertions[1].RstNOn_A	54832598	1085	0	0
gen_assertions[2].RstEnOff_A	27417545	13032	0	0
gen_assertions[2].RstEnOn_A	27417545	1069	0	0
gen_assertions[2].RstNOff_A	27417545	13032	0	0
gen_assertions[2].RstNOn_A	27417545	1069	0	0
gen_assertions[3].RstEnOff_A	27417270	13115	0	0
gen_assertions[3].RstEnOn_A	27417270	1151	0	0
gen_assertions[3].RstNOff_A	27417270	13115	0	0
gen_assertions[3].RstNOn_A	27417270	1151	0	0
gen_assertions[4].RstEnOff_A	1730935	22217	0	0
gen_assertions[4].RstEnOn_A	1730935	1156	0	0
gen_assertions[4].RstNOff_A	1730935	22217	0	0
gen_assertions[4].RstNOn_A	1730935	1156	0	0
gen_assertions[5].RstEnOff_A	13708244	14547	0	0
gen_assertions[5].RstEnOn_A	13708244	1213	0	0
gen_assertions[5].RstNOff_A	13708244	14547	0	0
gen_assertions[5].RstNOn_A	13708244	1213	0	0
gen_assertions[6].RstEnOff_A	13708244	14612	0	0
gen_assertions[6].RstEnOn_A	13708244	1271	0	0
gen_assertions[6].RstNOff_A	13708244	14612	0	0
gen_assertions[6].RstNOn_A	13708244	1271	0	0
gen_assertions[7].RstEnOff_A	13708244	14649	0	0
gen_assertions[7].RstEnOn_A	13708244	1305	0	0
gen_assertions[7].RstNOff_A	13708244	14649	0	0
gen_assertions[7].RstNOn_A	13708244	1305	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14336	0	0
T1	2881	5	0	0
T2	35376	45	0	0
T3	2954	5	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1148	0	0
T1	2881	1	0	0
T2	35376	0	0	0
T3	2954	1	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	1	0	0
T7	4946	1	0	0
T8	1262	0	0	0
T9	45350	0	0	0
T10	5987	0	0	0
T23	0	1	0	0
T45	0	4	0	0
T50	0	32	0	0
T51	0	28	0	0
T53	0	35	0	0
T62	0	16	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14336	0	0
T1	2881	5	0	0
T2	35376	45	0	0
T3	2954	5	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1148	0	0
T1	2881	1	0	0
T2	35376	0	0	0
T3	2954	1	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	1	0	0
T7	4946	1	0	0
T8	1262	0	0	0
T9	45350	0	0	0
T10	5987	0	0	0
T23	0	1	0	0
T45	0	4	0	0
T50	0	32	0	0
T51	0	28	0	0
T53	0	35	0	0
T62	0	16	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54832598	12994	0	0
T1	11522	5	0	0
T2	141502	42	0	0
T3	11815	4	0	0
T4	18189	0	0	0
T5	23289	0	0	0
T6	8852	4	0	0
T7	19790	15	0	0
T8	5050	0	0	0
T9	181389	70	0	0
T10	23947	4	0	0
T12	0	3	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54832598	1085	0	0
T1	11522	1	0	0
T2	141502	0	0	0
T3	11815	0	0	0
T4	18189	0	0	0
T5	23289	0	0	0
T6	8852	2	0	0
T7	19790	0	0	0
T8	5050	0	0	0
T9	181389	0	0	0
T10	23947	0	0	0
T23	0	2	0	0
T45	0	5	0	0
T49	0	2	0	0
T50	0	28	0	0
T51	0	31	0	0
T53	0	30	0	0
T62	0	17	0	0
T84	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54832598	12994	0	0
T1	11522	5	0	0
T2	141502	42	0	0
T3	11815	4	0	0
T4	18189	0	0	0
T5	23289	0	0	0
T6	8852	4	0	0
T7	19790	15	0	0
T8	5050	0	0	0
T9	181389	70	0	0
T10	23947	4	0	0
T12	0	3	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54832598	1085	0	0
T1	11522	1	0	0
T2	141502	0	0	0
T3	11815	0	0	0
T4	18189	0	0	0
T5	23289	0	0	0
T6	8852	2	0	0
T7	19790	0	0	0
T8	5050	0	0	0
T9	181389	0	0	0
T10	23947	0	0	0
T23	0	2	0	0
T45	0	5	0	0
T49	0	2	0	0
T50	0	28	0	0
T51	0	31	0	0
T53	0	30	0	0
T62	0	17	0	0
T84	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417545	13032	0	0
T1	5764	4	0	0
T2	70758	42	0	0
T3	5905	4	0	0
T4	9095	0	0	0
T5	11649	0	0	0
T6	4426	4	0	0
T7	9894	15	0	0
T8	2524	0	0	0
T9	90692	70	0	0
T10	11974	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417545	1069	0	0
T12	11666	1	0	0
T13	10023	0	0	0
T14	5112	0	0	0
T22	5289	0	0	0
T23	6108	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	8	0	0
T41	90989	0	0	0
T45	0	5	0	0
T49	0	2	0	0
T50	0	32	0	0
T51	185310	31	0	0
T52	11690	0	0	0
T53	258661	34	0	0
T54	3809	0	0	0
T62	0	14	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417545	13032	0	0
T1	5764	4	0	0
T2	70758	42	0	0
T3	5905	4	0	0
T4	9095	0	0	0
T5	11649	0	0	0
T6	4426	4	0	0
T7	9894	15	0	0
T8	2524	0	0	0
T9	90692	70	0	0
T10	11974	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417545	1069	0	0
T12	11666	1	0	0
T13	10023	0	0	0
T14	5112	0	0	0
T22	5289	0	0	0
T23	6108	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T38	0	8	0	0
T41	90989	0	0	0
T45	0	5	0	0
T49	0	2	0	0
T50	0	32	0	0
T51	185310	31	0	0
T52	11690	0	0	0
T53	258661	34	0	0
T54	3809	0	0	0
T62	0	14	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417270	13115	0	0
T1	5763	4	0	0
T2	70748	42	0	0
T3	5902	4	0	0
T4	9095	0	0	0
T5	11647	0	0	0
T6	4426	4	0	0
T7	9894	15	0	0
T8	2523	0	0	0
T9	90707	70	0	0
T10	11973	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417270	1151	0	0
T12	11666	1	0	0
T13	10023	0	0	0
T14	5112	0	0	0
T22	5286	0	0	0
T23	6108	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T38	0	6	0	0
T41	90976	0	0	0
T45	0	9	0	0
T49	0	4	0	0
T50	0	34	0	0
T51	185330	34	0	0
T52	11691	0	0	0
T53	258659	33	0	0
T54	3809	0	0	0
T62	0	12	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417270	13115	0	0
T1	5763	4	0	0
T2	70748	42	0	0
T3	5902	4	0	0
T4	9095	0	0	0
T5	11647	0	0	0
T6	4426	4	0	0
T7	9894	15	0	0
T8	2523	0	0	0
T9	90707	70	0	0
T10	11973	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27417270	1151	0	0
T12	11666	1	0	0
T13	10023	0	0	0
T14	5112	0	0	0
T22	5286	0	0	0
T23	6108	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T38	0	6	0	0
T41	90976	0	0	0
T45	0	9	0	0
T49	0	4	0	0
T50	0	34	0	0
T51	185330	34	0	0
T52	11691	0	0	0
T53	258659	33	0	0
T54	3809	0	0	0
T62	0	12	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	22217	0	0
T1	360	6	0	0
T2	4502	60	0	0
T3	368	7	0	0
T4	566	2	0	0
T5	730	3	0	0
T6	275	6	0	0
T7	617	18	0	0
T8	157	1	0	0
T9	5682	93	0	0
T10	748	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	1156	0	0
T3	368	1	0	0
T4	566	0	0	0
T5	730	0	0	0
T6	275	0	0	0
T7	617	0	0	0
T8	157	0	0	0
T9	5682	0	0	0
T10	748	0	0	0
T11	624	0	0	0
T21	202	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T45	0	8	0	0
T49	0	5	0	0
T50	0	32	0	0
T51	0	29	0	0
T53	0	33	0	0
T62	0	14	0	0
T85	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	22217	0	0
T1	360	6	0	0
T2	4502	60	0	0
T3	368	7	0	0
T4	566	2	0	0
T5	730	3	0	0
T6	275	6	0	0
T7	617	18	0	0
T8	157	1	0	0
T9	5682	93	0	0
T10	748	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730935	1156	0	0
T3	368	1	0	0
T4	566	0	0	0
T5	730	0	0	0
T6	275	0	0	0
T7	617	0	0	0
T8	157	0	0	0
T9	5682	0	0	0
T10	748	0	0	0
T11	624	0	0	0
T21	202	0	0	0
T35	0	5	0	0
T36	0	1	0	0
T45	0	8	0	0
T49	0	5	0	0
T50	0	32	0	0
T51	0	29	0	0
T53	0	33	0	0
T62	0	14	0	0
T85	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14547	0	0
T1	2881	4	0	0
T2	35376	45	0	0
T3	2954	4	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1213	0	0
T14	2556	0	0	0
T15	4859	0	0	0
T35	0	6	0	0
T38	0	10	0	0
T41	45492	0	0	0
T42	29117	0	0	0
T45	8422	11	0	0
T46	2265	0	0	0
T47	5854	0	0	0
T49	0	6	0	0
T50	0	26	0	0
T51	92659	25	0	0
T52	5843	0	0	0
T53	129333	34	0	0
T62	0	15	0	0
T86	0	1	0	0
T87	0	12	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14547	0	0
T1	2881	4	0	0
T2	35376	45	0	0
T3	2954	4	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1213	0	0
T14	2556	0	0	0
T15	4859	0	0	0
T35	0	6	0	0
T38	0	10	0	0
T41	45492	0	0	0
T42	29117	0	0	0
T45	8422	11	0	0
T46	2265	0	0	0
T47	5854	0	0	0
T49	0	6	0	0
T50	0	26	0	0
T51	92659	25	0	0
T52	5843	0	0	0
T53	129333	34	0	0
T62	0	15	0	0
T86	0	1	0	0
T87	0	12	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14612	0	0
T1	2881	4	0	0
T2	35376	45	0	0
T3	2954	4	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1271	0	0
T14	2556	0	0	0
T15	4859	0	0	0
T35	0	8	0	0
T36	0	1	0	0
T38	0	11	0	0
T41	45492	0	0	0
T42	29117	0	0	0
T45	8422	12	0	0
T46	2265	0	0	0
T47	5854	0	0	0
T49	0	7	0	0
T50	0	32	0	0
T51	92659	32	0	0
T52	5843	0	0	0
T53	129333	32	0	0
T62	0	14	0	0
T87	0	14	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14612	0	0
T1	2881	4	0	0
T2	35376	45	0	0
T3	2954	4	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1271	0	0
T14	2556	0	0	0
T15	4859	0	0	0
T35	0	8	0	0
T36	0	1	0	0
T38	0	11	0	0
T41	45492	0	0	0
T42	29117	0	0	0
T45	8422	12	0	0
T46	2265	0	0	0
T47	5854	0	0	0
T49	0	7	0	0
T50	0	32	0	0
T51	92659	32	0	0
T52	5843	0	0	0
T53	129333	32	0	0
T62	0	14	0	0
T87	0	14	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14649	0	0
T1	2881	4	0	0
T2	35376	45	0	0
T3	2954	4	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1305	0	0
T14	2556	0	0	0
T15	4859	0	0	0
T35	0	9	0	0
T38	0	14	0	0
T41	45492	0	0	0
T42	29117	0	0	0
T45	8422	12	0	0
T46	2265	0	0	0
T47	5854	0	0	0
T49	0	8	0	0
T50	0	35	0	0
T51	92659	29	0	0
T52	5843	0	0	0
T53	129333	25	0	0
T62	0	14	0	0
T75	0	8	0	0
T87	0	14	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	14649	0	0
T1	2881	4	0	0
T2	35376	45	0	0
T3	2954	4	0	0
T4	4547	0	0	0
T5	5826	0	0	0
T6	2211	6	0	0
T7	4946	17	0	0
T8	1262	0	0	0
T9	45350	75	0	0
T10	5987	4	0	0
T12	0	4	0	0
T22	0	4	0	0
T23	0	7	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13708244	1305	0	0
T14	2556	0	0	0
T15	4859	0	0	0
T35	0	9	0	0
T38	0	14	0	0
T41	45492	0	0	0
T42	29117	0	0	0
T45	8422	12	0	0
T46	2265	0	0	0
T47	5854	0	0	0
T49	0	8	0	0
T50	0	35	0	0
T51	92659	29	0	0
T52	5843	0	0	0
T53	129333	25	0	0
T62	0	14	0	0
T75	0	8	0	0
T87	0	14	0	0