Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12887568	7196	0	0
alert_regwen_rd_A	12887568	5792	0	0
cpu_regwen_rd_A	12887568	5719	0	0
sw_rst_ctrl_n_0_rd_A	12887568	10961	0	0
sw_rst_ctrl_n_1_rd_A	12887568	11223	0	0
sw_rst_ctrl_n_2_rd_A	12887568	10753	0	0
sw_rst_ctrl_n_3_rd_A	12887568	10819	0	0
sw_rst_ctrl_n_4_rd_A	12887568	11042	0	0
sw_rst_ctrl_n_5_rd_A	12887568	11002	0	0
sw_rst_ctrl_n_6_rd_A	12887568	10875	0	0
sw_rst_ctrl_n_7_rd_A	12887568	10879	0	0
sw_rst_regwen_0_rd_A	12887568	6484	0	0
sw_rst_regwen_1_rd_A	12887568	6552	0	0
sw_rst_regwen_2_rd_A	12887568	6276	0	0
sw_rst_regwen_3_rd_A	12887568	6414	0	0
sw_rst_regwen_4_rd_A	12887568	6399	0	0
sw_rst_regwen_5_rd_A	12887568	6588	0	0
sw_rst_regwen_6_rd_A	12887568	6356	0	0
sw_rst_regwen_7_rd_A	12887568	6265	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	7196	0	0
T63	19878	1	0	0
T65	16974	1	0	0
T66	18777	4	0	0
T67	7531	281	0	0
T68	4473	20	0	0
T69	2707	3	0	0
T88	9906	166	0	0
T89	4871	71	0	0
T90	9592	3	0	0
T92	2721	43	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	5792	0	0
T17	4503	0	0	0
T24	53083	0	0	0
T34	1616	0	0	0
T35	6949	0	0	0
T50	345432	551	0	0
T62	235288	0	0	0
T83	5298	0	0	0
T84	2086	0	0	0
T85	2555	0	0	0
T97	0	69	0	0
T98	0	160	0	0
T100	0	203	0	0
T120	0	311	0	0
T121	0	46	0	0
T122	0	71	0	0
T123	0	66	0	0
T124	0	217	0	0
T125	0	53	0	0
T126	1698	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	5719	0	0
T17	4503	0	0	0
T24	53083	0	0	0
T34	1616	0	0	0
T35	6949	0	0	0
T50	345432	581	0	0
T62	235288	0	0	0
T83	5298	0	0	0
T84	2086	0	0	0
T85	2555	0	0	0
T97	0	79	0	0
T98	0	145	0	0
T100	0	173	0	0
T120	0	293	0	0
T121	0	58	0	0
T122	0	61	0	0
T123	0	39	0	0
T124	0	185	0	0
T125	0	61	0	0
T126	1698	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	10961	0	0
T10	5888	18	0	0
T11	4897	0	0	0
T12	5641	16	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	1040	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	17	0	0
T97	0	82	0	0
T98	0	406	0	0
T100	0	401	0	0
T120	0	398	0	0
T121	0	83	0	0
T127	0	1	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	11223	0	0
T10	5888	17	0	0
T11	4897	0	0	0
T12	5641	9	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	1064	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	21	0	0
T97	0	59	0	0
T98	0	443	0	0
T100	0	402	0	0
T120	0	377	0	0
T121	0	88	0	0
T127	0	10	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	10753	0	0
T10	5888	10	0	0
T11	4897	0	0	0
T12	5641	14	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	968	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	10	0	0
T97	0	59	0	0
T98	0	464	0	0
T100	0	425	0	0
T120	0	379	0	0
T121	0	67	0	0
T127	0	13	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	10819	0	0
T10	5888	18	0	0
T11	4897	0	0	0
T12	5641	10	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	897	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	17	0	0
T97	0	59	0	0
T98	0	393	0	0
T100	0	411	0	0
T120	0	443	0	0
T121	0	68	0	0
T127	0	10	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	11042	0	0
T10	5888	15	0	0
T11	4897	0	0	0
T12	5641	15	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	1081	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	28	0	0
T97	0	80	0	0
T98	0	443	0	0
T100	0	488	0	0
T120	0	429	0	0
T121	0	46	0	0
T127	0	8	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	11002	0	0
T10	5888	14	0	0
T11	4897	0	0	0
T12	5641	15	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	957	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	8	0	0
T97	0	83	0	0
T98	0	468	0	0
T100	0	371	0	0
T120	0	380	0	0
T121	0	67	0	0
T127	0	12	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	10875	0	0
T10	5888	8	0	0
T11	4897	0	0	0
T12	5641	15	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	902	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	12	0	0
T97	0	86	0	0
T98	0	468	0	0
T100	0	431	0	0
T120	0	392	0	0
T121	0	72	0	0
T122	0	63	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	10879	0	0
T10	5888	8	0	0
T11	4897	0	0	0
T12	5641	6	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	1026	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T80	0	23	0	0
T97	0	55	0	0
T98	0	414	0	0
T100	0	380	0	0
T120	0	403	0	0
T121	0	64	0	0
T127	0	3	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6484	0	0
T10	5888	3	0	0
T11	4897	0	0	0
T12	5641	0	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	591	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	67	0	0
T98	0	156	0	0
T100	0	240	0	0
T120	0	378	0	0
T121	0	57	0	0
T122	0	75	0	0
T123	0	83	0	0
T124	0	164	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6552	0	0
T10	5888	2	0	0
T11	4897	0	0	0
T12	5641	10	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	563	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	73	0	0
T98	0	141	0	0
T100	0	193	0	0
T120	0	372	0	0
T121	0	85	0	0
T122	0	59	0	0
T123	0	66	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6276	0	0
T10	5888	8	0	0
T11	4897	0	0	0
T12	5641	15	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	546	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	82	0	0
T98	0	176	0	0
T100	0	195	0	0
T120	0	349	0	0
T121	0	68	0	0
T122	0	70	0	0
T123	0	50	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6414	0	0
T10	5888	2	0	0
T11	4897	0	0	0
T12	5641	9	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	556	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	89	0	0
T98	0	172	0	0
T100	0	209	0	0
T120	0	349	0	0
T121	0	72	0	0
T122	0	73	0	0
T123	0	76	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6399	0	0
T10	5888	7	0	0
T11	4897	0	0	0
T12	5641	4	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	548	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	71	0	0
T98	0	169	0	0
T100	0	218	0	0
T120	0	360	0	0
T121	0	96	0	0
T122	0	71	0	0
T123	0	67	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6588	0	0
T10	5888	10	0	0
T11	4897	0	0	0
T12	5641	3	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	587	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	54	0	0
T98	0	171	0	0
T100	0	228	0	0
T120	0	407	0	0
T121	0	74	0	0
T122	0	66	0	0
T123	0	67	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6356	0	0
T10	5888	16	0	0
T11	4897	0	0	0
T12	5641	10	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	525	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	51	0	0
T98	0	163	0	0
T100	0	211	0	0
T120	0	354	0	0
T121	0	51	0	0
T122	0	65	0	0
T123	0	68	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12887568	6265	0	0
T10	5888	4	0	0
T11	4897	0	0	0
T12	5641	15	0	0
T13	4896	0	0	0
T14	2441	0	0	0
T21	1610	0	0	0
T22	2449	0	0	0
T23	2658	0	0	0
T50	0	550	0	0
T51	73875	0	0	0
T54	1813	0	0	0
T97	0	67	0	0
T98	0	182	0	0
T100	0	223	0	0
T120	0	344	0	0
T121	0	66	0	0
T122	0	77	0	0
T123	0	65	0	0