Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651356	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

392520

1

T1

74

T2

2

T3

838

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	556859	1			T1	99		T3	1281		T4	99
values[0x0]	243005	1			T1	60		T2	2		T3	503
values[0x1]	244012	1			T1	53		T2	11		T3	497

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	546699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

497177

1

T1

90

T2

3

T3

1091

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4130	1			T7	2		T10	14		T11	1
valid_sources[0x01]	4295	1			T6	1		T10	13		T11	4
valid_sources[0x02]	3510	1			T6	1		T7	3		T10	9
valid_sources[0x03]	3513	1			T3	12		T7	4		T10	14
valid_sources[0x04]	4132	1			T7	1		T10	15		T11	3
valid_sources[0x05]	3340	1			T10	9		T11	2		T22	3
valid_sources[0x06]	3397	1			T7	1		T10	5		T11	1
valid_sources[0x07]	3360	1			T3	3		T10	12		T11	3
valid_sources[0x08]	4272	1			T6	1		T7	1		T10	9
valid_sources[0x09]	3406	1			T10	7		T11	1		T22	20
valid_sources[0x0a]	4365	1			T3	70		T6	1		T7	1
valid_sources[0x0b]	4321	1			T1	212		T6	1		T10	3
valid_sources[0x0c]	4294	1			T10	10		T22	10		T23	1
valid_sources[0x0d]	3791	1			T7	1		T10	11		T11	4
valid_sources[0x0e]	3804	1			T7	1		T10	11		T11	3
valid_sources[0x0f]	3269	1			T7	1		T10	13		T11	1
valid_sources[0x10]	3752	1			T10	11		T33	59		T36	2
valid_sources[0x11]	3773	1			T7	4		T10	9		T11	1
valid_sources[0x12]	3861	1			T6	2		T7	1		T10	9
valid_sources[0x13]	3951	1			T6	1		T10	12		T11	2
valid_sources[0x14]	3417	1			T10	10		T11	3		T58	2
valid_sources[0x15]	6947	1			T7	1		T10	4		T33	152
valid_sources[0x16]	4259	1			T6	2		T7	1		T10	13
valid_sources[0x17]	5032	1			T10	9		T11	2		T33	33
valid_sources[0x18]	3707	1			T6	2		T9	212		T10	11
valid_sources[0x19]	3061	1			T6	1		T10	12		T36	8
valid_sources[0x1a]	4660	1			T6	3		T10	7		T11	3
valid_sources[0x1b]	3456	1			T3	70		T6	1		T7	2
valid_sources[0x1c]	3296	1			T6	2		T10	6		T11	1
valid_sources[0x1d]	3781	1			T7	3		T10	13		T11	2
valid_sources[0x1e]	3353	1			T6	3		T10	13		T11	1
valid_sources[0x1f]	3610	1			T6	1		T7	1		T10	16
valid_sources[0x20]	5138	1			T2	2		T6	2		T10	9
valid_sources[0x21]	3903	1			T3	112		T6	1		T7	4
valid_sources[0x22]	3561	1			T3	139		T6	2		T7	4
valid_sources[0x23]	4529	1			T7	1		T10	8		T22	13
valid_sources[0x24]	4238	1			T6	1		T10	10		T11	4
valid_sources[0x25]	3801	1			T6	1		T10	11		T11	4
valid_sources[0x26]	3911	1			T10	5		T11	1		T22	9
valid_sources[0x27]	4382	1			T10	8		T11	1		T33	167
valid_sources[0x28]	3685	1			T2	2		T3	113		T10	12
valid_sources[0x29]	4514	1			T6	1		T7	1		T10	7
valid_sources[0x2a]	3218	1			T6	2		T10	12		T11	1
valid_sources[0x2b]	5590	1			T6	1		T7	1		T10	18
valid_sources[0x2c]	3537	1			T10	8		T11	1		T22	5
valid_sources[0x2d]	4647	1			T3	325		T6	2		T7	2
valid_sources[0x2e]	3521	1			T10	8		T58	10		T83	2
valid_sources[0x2f]	3726	1			T10	8		T11	2		T22	49
valid_sources[0x30]	3496	1			T6	1		T10	9		T11	1
valid_sources[0x31]	3959	1			T10	10		T11	1		T38	1
valid_sources[0x32]	3607	1			T6	1		T10	10		T11	3
valid_sources[0x33]	7011	1			T3	171		T7	2		T10	11
valid_sources[0x34]	4048	1			T6	1		T7	2		T10	13
valid_sources[0x35]	4113	1			T6	1		T10	17		T11	1
valid_sources[0x36]	3588	1			T6	2		T10	12		T11	1
valid_sources[0x37]	3786	1			T6	1		T10	10		T11	2
valid_sources[0x38]	3820	1			T6	3		T7	2		T10	16
valid_sources[0x39]	4158	1			T6	1		T10	8		T11	1
valid_sources[0x3a]	4344	1			T7	7		T10	13		T11	3
valid_sources[0x3b]	4532	1			T6	1		T10	9		T11	1
valid_sources[0x3c]	3993	1			T3	11		T7	2		T10	12
valid_sources[0x3d]	3932	1			T6	2		T10	11		T11	2
valid_sources[0x3e]	4966	1			T6	1		T10	14		T11	1
valid_sources[0x3f]	4590	1			T10	9		T11	2		T22	2
valid_sources[0x40]	4353	1			T6	2		T10	9		T11	2
valid_sources[0x41]	3974	1			T10	15		T11	1		T22	21
valid_sources[0x42]	3610	1			T10	10		T36	2		T58	3
valid_sources[0x43]	3339	1			T7	1		T10	12		T11	2
valid_sources[0x44]	7612	1			T6	2		T7	2		T10	8
valid_sources[0x45]	3831	1			T10	5		T11	1		T22	26
valid_sources[0x46]	3216	1			T6	1		T7	2		T10	10
valid_sources[0x47]	3367	1			T10	10		T22	6		T36	1
valid_sources[0x48]	4196	1			T6	1		T7	1		T10	14
valid_sources[0x49]	3511	1			T6	1		T10	8		T11	1
valid_sources[0x4a]	4132	1			T10	4		T22	16		T36	11
valid_sources[0x4b]	3962	1			T10	10		T22	3		T36	4
valid_sources[0x4c]	3941	1			T6	1		T10	15		T11	1
valid_sources[0x4d]	3525	1			T3	70		T6	1		T7	2
valid_sources[0x4e]	6323	1			T8	3200		T10	11		T38	2
valid_sources[0x4f]	3965	1			T7	1		T10	13		T11	1
valid_sources[0x50]	3482	1			T10	5		T11	4		T38	3
valid_sources[0x51]	3732	1			T6	1		T7	1		T10	10
valid_sources[0x52]	5551	1			T10	4		T11	2		T22	10
valid_sources[0x53]	3363	1			T7	1		T10	8		T11	3
valid_sources[0x54]	3674	1			T3	311		T7	3		T10	9
valid_sources[0x55]	3760	1			T6	2		T10	9		T11	1
valid_sources[0x56]	5356	1			T6	1		T10	11		T11	1
valid_sources[0x57]	3599	1			T6	1		T7	1		T10	13
valid_sources[0x58]	3906	1			T7	1		T10	13		T22	49
valid_sources[0x59]	3962	1			T2	2		T6	1		T7	4
valid_sources[0x5a]	4105	1			T6	2		T10	12		T11	2
valid_sources[0x5b]	3998	1			T7	1		T10	19		T22	10
valid_sources[0x5c]	3914	1			T3	284		T6	1		T7	5
valid_sources[0x5d]	3831	1			T7	3		T10	8		T22	32
valid_sources[0x5e]	3745	1			T6	1		T10	8		T11	2
valid_sources[0x5f]	5226	1			T7	1		T10	14		T11	2
valid_sources[0x60]	7515	1			T10	12		T11	5		T22	45
valid_sources[0x61]	3715	1			T6	1		T7	1		T10	11
valid_sources[0x62]	3591	1			T6	1		T10	10		T11	2
valid_sources[0x63]	4904	1			T6	1		T7	2		T10	10
valid_sources[0x64]	4020	1			T6	2		T10	9		T11	1
valid_sources[0x65]	4397	1			T7	2		T10	7		T22	32
valid_sources[0x66]	4086	1			T6	3		T7	1		T10	13
valid_sources[0x67]	3850	1			T7	1		T10	8		T11	4
valid_sources[0x68]	3834	1			T6	1		T7	3		T10	10
valid_sources[0x69]	4151	1			T6	3		T7	1		T10	10
valid_sources[0x6a]	3619	1			T6	1		T7	1		T10	17
valid_sources[0x6b]	3873	1			T6	1		T10	13		T11	2
valid_sources[0x6c]	4367	1			T7	1		T10	7		T11	3
valid_sources[0x6d]	4121	1			T10	7		T23	1		T33	88
valid_sources[0x6e]	4184	1			T10	11		T11	2		T33	58
valid_sources[0x6f]	3414	1			T6	1		T7	1		T10	8
valid_sources[0x70]	4501	1			T7	2		T10	14		T11	3
valid_sources[0x71]	3886	1			T6	3		T7	1		T10	9
valid_sources[0x72]	4879	1			T10	15		T11	1		T22	5
valid_sources[0x73]	3662	1			T6	1		T7	2		T10	9
valid_sources[0x74]	4265	1			T3	55		T6	1		T7	1
valid_sources[0x75]	3326	1			T10	12		T11	1		T22	12
valid_sources[0x76]	3708	1			T6	1		T7	3		T10	9
valid_sources[0x77]	4369	1			T6	1		T10	14		T11	1
valid_sources[0x78]	3984	1			T6	1		T10	10		T11	2
valid_sources[0x79]	3167	1			T7	3		T10	13		T11	1
valid_sources[0x7a]	6878	1			T7	1		T10	11		T11	2
valid_sources[0x7b]	3817	1			T6	2		T7	1		T10	11
valid_sources[0x7c]	3669	1			T3	1		T6	1		T7	5
valid_sources[0x7d]	3909	1			T6	1		T7	3		T10	11
valid_sources[0x7e]	3672	1			T7	2		T10	6		T22	20
valid_sources[0x7f]	4088	1			T10	15		T11	1		T58	8
valid_sources[0x80]	4304	1			T6	2		T10	7		T22	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

261803

1

T1

44

T3

561

T4

37

values[0x0]

all_enables

biggest_size

84866

1

T1

21

T3

184

T4

13

values[0x1]

all_enables

biggest_size

45851

1

T1

9

T2

2

T3

93