Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T10,T33
1	0	Covered	T3,T10,T33

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T8
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56147901	9711	0	0
CascadeEffAonToRstPorAboveRise_A	56147901	9711	0	0
CascadeEffAonToRstPorIoAboveFall_A	53900225	9711	0	0
CascadeEffAonToRstPorIoAboveRise_A	53900225	9711	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26951243	9711	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26951243	9711	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13475397	9711	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13475397	9711	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26950981	9711	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26950981	9711	0	0
CascadeLcToLcAboveFall_A	56147901	23607	0	0
CascadeLcToLcAboveRise_A	56147901	23607	0	0
CascadeLcToLcAonAboveFall_A	1702879	23607	0	0
CascadeLcToLcAonAboveRise_A	1702879	23607	0	0
CascadeLcToLcShadowedAboveFall_A	56147901	23607	0	0
CascadeLcToLcShadowedAboveRise_A	56147901	23607	0	0
CascadePorToAonAboveFall_A	1702879	7825	0	0
CascadeSysToSysAboveFall_A	56147901	23607	0	0
CascadeSysToSysAboveRise_A	56147901	23607	0	0
ScanRstToAonRise_A	1702879	242	0	0
StablePorToAonRise_A	1702879	9711	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11829939	23607	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11829939	23607	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11829939	23607	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11829939	23607	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13475397	23607	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13475397	23607	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11829939	23607	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11829939	23607	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11829939	23607	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11829939	23607	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	9711	0	0
T1	17285	2	0	0
T2	7042	1	0	0
T3	137094	16	0	0
T4	9761	2	0	0
T5	22273	2	0	0
T6	14392	2	0	0
T7	23272	1	0	0
T8	121864	27	0	0
T9	15485	2	0	0
T10	141585	19	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	9711	0	0
T1	17285	2	0	0
T2	7042	1	0	0
T3	137094	16	0	0
T4	9761	2	0	0
T5	22273	2	0	0
T6	14392	2	0	0
T7	23272	1	0	0
T8	121864	27	0	0
T9	15485	2	0	0
T10	141585	19	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53900225	9711	0	0
T1	16586	2	0	0
T2	6761	1	0	0
T3	131620	16	0	0
T4	9371	2	0	0
T5	21381	2	0	0
T6	13814	2	0	0
T7	22339	1	0	0
T8	116997	27	0	0
T9	14867	2	0	0
T10	135897	19	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53900225	9711	0	0
T1	16586	2	0	0
T2	6761	1	0	0
T3	131620	16	0	0
T4	9371	2	0	0
T5	21381	2	0	0
T6	13814	2	0	0
T7	22339	1	0	0
T8	116997	27	0	0
T9	14867	2	0	0
T10	135897	19	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26951243	9711	0	0
T1	8294	2	0	0
T2	3379	1	0	0
T3	65805	16	0	0
T4	4684	2	0	0
T5	10690	2	0	0
T6	6905	2	0	0
T7	11171	1	0	0
T8	58513	27	0	0
T9	7435	2	0	0
T10	67952	19	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26951243	9711	0	0
T1	8294	2	0	0
T2	3379	1	0	0
T3	65805	16	0	0
T4	4684	2	0	0
T5	10690	2	0	0
T6	6905	2	0	0
T7	11171	1	0	0
T8	58513	27	0	0
T9	7435	2	0	0
T10	67952	19	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	9711	0	0
T1	4146	2	0	0
T2	1690	1	0	0
T3	32905	16	0	0
T4	2340	2	0	0
T5	5345	2	0	0
T6	3454	2	0	0
T7	5585	1	0	0
T8	29255	27	0	0
T9	3717	2	0	0
T10	33977	19	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	9711	0	0
T1	4146	2	0	0
T2	1690	1	0	0
T3	32905	16	0	0
T4	2340	2	0	0
T5	5345	2	0	0
T6	3454	2	0	0
T7	5585	1	0	0
T8	29255	27	0	0
T9	3717	2	0	0
T10	33977	19	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26950981	9711	0	0
T1	8294	2	0	0
T2	3380	1	0	0
T3	65805	16	0	0
T4	4681	2	0	0
T5	10690	2	0	0
T6	6907	2	0	0
T7	11171	1	0	0
T8	58510	27	0	0
T9	7433	2	0	0
T10	67952	19	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26950981	9711	0	0
T1	8294	2	0	0
T2	3380	1	0	0
T3	65805	16	0	0
T4	4681	2	0	0
T5	10690	2	0	0
T6	6907	2	0	0
T7	11171	1	0	0
T8	58510	27	0	0
T9	7433	2	0	0
T10	67952	19	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	23607	0	0
T1	17285	6	0	0
T2	7042	1	0	0
T3	137094	45	0	0
T4	9761	6	0	0
T5	22273	2	0	0
T6	14392	6	0	0
T7	23272	15	0	0
T8	121864	102	0	0
T9	15485	6	0	0
T10	141585	52	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	23607	0	0
T1	17285	6	0	0
T2	7042	1	0	0
T3	137094	45	0	0
T4	9761	6	0	0
T5	22273	2	0	0
T6	14392	6	0	0
T7	23272	15	0	0
T8	121864	102	0	0
T9	15485	6	0	0
T10	141585	52	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	23607	0	0
T1	517	6	0	0
T2	210	1	0	0
T3	4156	45	0	0
T4	291	6	0	0
T5	666	2	0	0
T6	430	6	0	0
T7	696	15	0	0
T8	3671	102	0	0
T9	464	6	0	0
T10	4294	52	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	23607	0	0
T1	517	6	0	0
T2	210	1	0	0
T3	4156	45	0	0
T4	291	6	0	0
T5	666	2	0	0
T6	430	6	0	0
T7	696	15	0	0
T8	3671	102	0	0
T9	464	6	0	0
T10	4294	52	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	23607	0	0
T1	17285	6	0	0
T2	7042	1	0	0
T3	137094	45	0	0
T4	9761	6	0	0
T5	22273	2	0	0
T6	14392	6	0	0
T7	23272	15	0	0
T8	121864	102	0	0
T9	15485	6	0	0
T10	141585	52	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	23607	0	0
T1	17285	6	0	0
T2	7042	1	0	0
T3	137094	45	0	0
T4	9761	6	0	0
T5	22273	2	0	0
T6	14392	6	0	0
T7	23272	15	0	0
T8	121864	102	0	0
T9	15485	6	0	0
T10	141585	52	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	7825	0	0
T1	517	1	0	0
T2	210	1	0	0
T3	4156	7	0	0
T4	291	1	0	0
T5	666	19	0	0
T6	430	1	0	0
T7	696	1	0	0
T8	3671	27	0	0
T9	464	1	0	0
T10	4294	7	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	23607	0	0
T1	17285	6	0	0
T2	7042	1	0	0
T3	137094	45	0	0
T4	9761	6	0	0
T5	22273	2	0	0
T6	14392	6	0	0
T7	23272	15	0	0
T8	121864	102	0	0
T9	15485	6	0	0
T10	141585	52	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56147901	23607	0	0
T1	17285	6	0	0
T2	7042	1	0	0
T3	137094	45	0	0
T4	9761	6	0	0
T5	22273	2	0	0
T6	14392	6	0	0
T7	23272	15	0	0
T8	121864	102	0	0
T9	15485	6	0	0
T10	141585	52	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	242	0	0
T3	4156	1	0	0
T4	291	0	0	0
T5	666	0	0	0
T6	430	0	0	0
T7	696	0	0	0
T8	3671	0	0	0
T9	464	0	0	0
T10	4294	1	0	0
T11	816	0	0	0
T21	643	0	0	0
T33	0	1	0	0
T39	0	4	0	0
T48	0	2	0	0
T82	0	2	0	0
T91	0	1	0	0
T100	0	8	0	0
T101	0	1	0	0
T136	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	9711	0	0
T1	517	2	0	0
T2	210	1	0	0
T3	4156	16	0	0
T4	291	2	0	0
T5	666	2	0	0
T6	430	2	0	0
T7	696	1	0	0
T8	3671	27	0	0
T9	464	2	0	0
T10	4294	19	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	23607	0	0
T1	4146	6	0	0
T2	1690	1	0	0
T3	32905	45	0	0
T4	2340	6	0	0
T5	5345	2	0	0
T6	3454	6	0	0
T7	5585	15	0	0
T8	29255	102	0	0
T9	3717	6	0	0
T10	33977	52	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	23607	0	0
T1	4146	6	0	0
T2	1690	1	0	0
T3	32905	45	0	0
T4	2340	6	0	0
T5	5345	2	0	0
T6	3454	6	0	0
T7	5585	15	0	0
T8	29255	102	0	0
T9	3717	6	0	0
T10	33977	52	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11829939	23607	0	0
T1	3814	6	0	0
T2	1623	1	0	0
T3	29131	45	0	0
T4	2152	6	0	0
T5	5254	2	0	0
T6	3211	6	0	0
T7	4439	15	0	0
T8	26118	102	0	0
T9	3384	6	0	0
T10	28556	52	0	0