Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T21
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T34,T36
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T34,T36
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T34,T36
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T34,T36
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T34,T36
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T34,T36
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T34,T36
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13475397	14880	0	0
gen_assertions[0].RstEnOn_A	13475397	1160	0	0
gen_assertions[0].RstNOff_A	13475397	14880	0	0
gen_assertions[0].RstNOn_A	13475397	1160	0	0
gen_assertions[1].RstEnOff_A	53900225	13531	0	0
gen_assertions[1].RstEnOn_A	53900225	1094	0	0
gen_assertions[1].RstNOff_A	53900225	13531	0	0
gen_assertions[1].RstNOn_A	53900225	1094	0	0
gen_assertions[2].RstEnOff_A	26951243	13582	0	0
gen_assertions[2].RstEnOn_A	26951243	1088	0	0
gen_assertions[2].RstNOff_A	26951243	13582	0	0
gen_assertions[2].RstNOn_A	26951243	1088	0	0
gen_assertions[3].RstEnOff_A	26950981	13657	0	0
gen_assertions[3].RstEnOn_A	26950981	1166	0	0
gen_assertions[3].RstNOff_A	26950981	13657	0	0
gen_assertions[3].RstNOn_A	26950981	1166	0	0
gen_assertions[4].RstEnOff_A	1702879	23473	0	0
gen_assertions[4].RstEnOn_A	1702879	1208	0	0
gen_assertions[4].RstNOff_A	1702879	23473	0	0
gen_assertions[4].RstNOn_A	1702879	1208	0	0
gen_assertions[5].RstEnOff_A	13475397	15121	0	0
gen_assertions[5].RstEnOn_A	13475397	1261	0	0
gen_assertions[5].RstNOff_A	13475397	15121	0	0
gen_assertions[5].RstNOn_A	13475397	1261	0	0
gen_assertions[6].RstEnOff_A	13475397	15176	0	0
gen_assertions[6].RstEnOn_A	13475397	1319	0	0
gen_assertions[6].RstNOff_A	13475397	15176	0	0
gen_assertions[6].RstNOn_A	13475397	1319	0	0
gen_assertions[7].RstEnOff_A	13475397	15196	0	0
gen_assertions[7].RstEnOn_A	13475397	1345	0	0
gen_assertions[7].RstNOff_A	13475397	15196	0	0
gen_assertions[7].RstNOn_A	13475397	1345	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	14880	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1160	0	0
T7	5585	4	0	0
T8	29255	0	0	0
T9	3717	0	0	0
T10	33977	0	0	0
T11	6529	3	0	0
T21	5152	0	0	0
T22	29470	0	0	0
T23	1858	0	0	0
T33	37431	31	0	0
T34	2783	1	0	0
T36	0	6	0	0
T38	0	8	0	0
T39	0	25	0	0
T58	0	2	0	0
T83	0	1	0	0
T87	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	14880	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1160	0	0
T7	5585	4	0	0
T8	29255	0	0	0
T9	3717	0	0	0
T10	33977	0	0	0
T11	6529	3	0	0
T21	5152	0	0	0
T22	29470	0	0	0
T23	1858	0	0	0
T33	37431	31	0	0
T34	2783	1	0	0
T36	0	6	0	0
T38	0	8	0	0
T39	0	25	0	0
T58	0	2	0	0
T83	0	1	0	0
T87	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53900225	13531	0	0
T1	16586	4	0	0
T2	6761	0	0	0
T3	131620	25	0	0
T4	9371	2	0	0
T5	21381	0	0	0
T6	13814	4	0	0
T7	22339	11	0	0
T8	116997	68	0	0
T9	14867	2	0	0
T10	135897	31	0	0
T11	0	19	0	0
T21	0	14	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53900225	1094	0	0
T12	21728	0	0	0
T33	149743	29	0	0
T34	11136	2	0	0
T35	14069	0	0	0
T36	34800	10	0	0
T37	225800	0	0	0
T38	16880	13	0	0
T39	392491	23	0	0
T58	24729	1	0	0
T87	22490	0	0	0
T88	0	4	0	0
T89	0	3	0	0
T90	0	9	0	0
T91	0	10	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53900225	13531	0	0
T1	16586	4	0	0
T2	6761	0	0	0
T3	131620	25	0	0
T4	9371	2	0	0
T5	21381	0	0	0
T6	13814	4	0	0
T7	22339	11	0	0
T8	116997	68	0	0
T9	14867	2	0	0
T10	135897	31	0	0
T11	0	19	0	0
T21	0	14	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53900225	1094	0	0
T12	21728	0	0	0
T33	149743	29	0	0
T34	11136	2	0	0
T35	14069	0	0	0
T36	34800	10	0	0
T37	225800	0	0	0
T38	16880	13	0	0
T39	392491	23	0	0
T58	24729	1	0	0
T87	22490	0	0	0
T88	0	4	0	0
T89	0	3	0	0
T90	0	9	0	0
T91	0	10	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26951243	13582	0	0
T1	8294	4	0	0
T2	3379	0	0	0
T3	65805	25	0	0
T4	4684	2	0	0
T5	10690	0	0	0
T6	6905	4	0	0
T7	11171	11	0	0
T8	58513	68	0	0
T9	7435	2	0	0
T10	67952	31	0	0
T11	0	19	0	0
T21	0	14	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26951243	1088	0	0
T12	10864	0	0	0
T33	74872	31	0	0
T34	5567	2	0	0
T35	7032	0	0	0
T36	17401	8	0	0
T37	112924	0	0	0
T38	8441	1	0	0
T39	196234	25	0	0
T58	12365	4	0	0
T87	11244	0	0	0
T88	0	6	0	0
T89	0	4	0	0
T90	0	9	0	0
T92	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26951243	13582	0	0
T1	8294	4	0	0
T2	3379	0	0	0
T3	65805	25	0	0
T4	4684	2	0	0
T5	10690	0	0	0
T6	6905	4	0	0
T7	11171	11	0	0
T8	58513	68	0	0
T9	7435	2	0	0
T10	67952	31	0	0
T11	0	19	0	0
T21	0	14	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26951243	1088	0	0
T12	10864	0	0	0
T33	74872	31	0	0
T34	5567	2	0	0
T35	7032	0	0	0
T36	17401	8	0	0
T37	112924	0	0	0
T38	8441	1	0	0
T39	196234	25	0	0
T58	12365	4	0	0
T87	11244	0	0	0
T88	0	6	0	0
T89	0	4	0	0
T90	0	9	0	0
T92	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26950981	13657	0	0
T1	8294	4	0	0
T2	3380	0	0	0
T3	65805	25	0	0
T4	4681	2	0	0
T5	10690	0	0	0
T6	6907	4	0	0
T7	11171	11	0	0
T8	58510	68	0	0
T9	7433	2	0	0
T10	67952	31	0	0
T11	0	19	0	0
T21	0	14	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26950981	1166	0	0
T12	10864	0	0	0
T33	74865	25	0	0
T34	5568	4	0	0
T35	7030	0	0	0
T36	17400	12	0	0
T37	112909	0	0	0
T38	8440	0	0	0
T39	196241	25	0	0
T58	12365	3	0	0
T87	11244	0	0	0
T88	0	8	0	0
T89	0	5	0	0
T90	0	10	0	0
T91	0	16	0	0
T92	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26950981	13657	0	0
T1	8294	4	0	0
T2	3380	0	0	0
T3	65805	25	0	0
T4	4681	2	0	0
T5	10690	0	0	0
T6	6907	4	0	0
T7	11171	11	0	0
T8	58510	68	0	0
T9	7433	2	0	0
T10	67952	31	0	0
T11	0	19	0	0
T21	0	14	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26950981	1166	0	0
T12	10864	0	0	0
T33	74865	25	0	0
T34	5568	4	0	0
T35	7030	0	0	0
T36	17400	12	0	0
T37	112909	0	0	0
T38	8440	0	0	0
T39	196241	25	0	0
T58	12365	3	0	0
T87	11244	0	0	0
T88	0	8	0	0
T89	0	5	0	0
T90	0	10	0	0
T91	0	16	0	0
T92	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	23473	0	0
T1	517	6	0	0
T2	210	1	0	0
T3	4156	43	0	0
T4	291	4	0	0
T5	666	2	0	0
T6	430	6	0	0
T7	696	15	0	0
T8	3671	74	0	0
T9	464	4	0	0
T10	4294	52	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	1208	0	0
T12	677	0	0	0
T33	4768	32	0	0
T34	347	5	0	0
T35	438	0	0	0
T36	1086	11	0	0
T37	7072	0	0	0
T38	526	0	0	0
T39	12556	20	0	0
T58	772	4	0	0
T83	0	1	0	0
T87	701	0	0	0
T88	0	8	0	0
T89	0	7	0	0
T90	0	10	0	0
T91	0	17	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	23473	0	0
T1	517	6	0	0
T2	210	1	0	0
T3	4156	43	0	0
T4	291	4	0	0
T5	666	2	0	0
T6	430	6	0	0
T7	696	15	0	0
T8	3671	74	0	0
T9	464	4	0	0
T10	4294	52	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1702879	1208	0	0
T12	677	0	0	0
T33	4768	32	0	0
T34	347	5	0	0
T35	438	0	0	0
T36	1086	11	0	0
T37	7072	0	0	0
T38	526	0	0	0
T39	12556	20	0	0
T58	772	4	0	0
T83	0	1	0	0
T87	701	0	0	0
T88	0	8	0	0
T89	0	7	0	0
T90	0	10	0	0
T91	0	17	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	15121	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1261	0	0
T12	5432	0	0	0
T33	37431	32	0	0
T34	2783	6	0	0
T35	3515	0	0	0
T36	8699	13	0	0
T37	56455	0	0	0
T38	4220	0	0	0
T39	98115	23	0	0
T58	6181	7	0	0
T87	5622	0	0	0
T88	0	11	0	0
T89	0	9	0	0
T90	0	13	0	0
T91	0	17	0	0
T93	0	15	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	15121	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1261	0	0
T12	5432	0	0	0
T33	37431	32	0	0
T34	2783	6	0	0
T35	3515	0	0	0
T36	8699	13	0	0
T37	56455	0	0	0
T38	4220	0	0	0
T39	98115	23	0	0
T58	6181	7	0	0
T87	5622	0	0	0
T88	0	11	0	0
T89	0	9	0	0
T90	0	13	0	0
T91	0	17	0	0
T93	0	15	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	15176	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1319	0	0
T12	5432	0	0	0
T33	37431	32	0	0
T34	2783	7	0	0
T35	3515	0	0	0
T36	8699	13	0	0
T37	56455	0	0	0
T38	4220	0	0	0
T39	98115	23	0	0
T58	6181	7	0	0
T87	5622	0	0	0
T88	0	11	0	0
T89	0	10	0	0
T90	0	14	0	0
T91	0	15	0	0
T93	0	14	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	15176	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1319	0	0
T12	5432	0	0	0
T33	37431	32	0	0
T34	2783	7	0	0
T35	3515	0	0	0
T36	8699	13	0	0
T37	56455	0	0	0
T38	4220	0	0	0
T39	98115	23	0	0
T58	6181	7	0	0
T87	5622	0	0	0
T88	0	11	0	0
T89	0	10	0	0
T90	0	14	0	0
T91	0	15	0	0
T93	0	14	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	15196	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1345	0	0
T12	5432	0	0	0
T33	37431	30	0	0
T34	2783	8	0	0
T35	3515	0	0	0
T36	8699	14	0	0
T37	56455	0	0	0
T38	4220	0	0	0
T39	98115	24	0	0
T58	6181	8	0	0
T83	0	1	0	0
T87	5622	0	0	0
T88	0	11	0	0
T89	0	9	0	0
T90	0	10	0	0
T91	0	15	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	15196	0	0
T1	4146	4	0	0
T2	1690	0	0	0
T3	32905	29	0	0
T4	2340	4	0	0
T5	5345	0	0	0
T6	3454	4	0	0
T7	5585	14	0	0
T8	29255	75	0	0
T9	3717	4	0	0
T10	33977	33	0	0
T11	0	19	0	0
T21	0	16	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13475397	1345	0	0
T12	5432	0	0	0
T33	37431	30	0	0
T34	2783	8	0	0
T35	3515	0	0	0
T36	8699	14	0	0
T37	56455	0	0	0
T38	4220	0	0	0
T39	98115	24	0	0
T58	6181	8	0	0
T83	0	1	0	0
T87	5622	0	0	0
T88	0	11	0	0
T89	0	9	0	0
T90	0	10	0	0
T91	0	15	0	0