Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12673530	7490	0	0
alert_regwen_rd_A	12673530	5461	0	0
cpu_regwen_rd_A	12673530	5392	0	0
sw_rst_ctrl_n_0_rd_A	12673530	8218	0	0
sw_rst_ctrl_n_1_rd_A	12673530	8547	0	0
sw_rst_ctrl_n_2_rd_A	12673530	8386	0	0
sw_rst_ctrl_n_3_rd_A	12673530	8644	0	0
sw_rst_ctrl_n_4_rd_A	12673530	8416	0	0
sw_rst_ctrl_n_5_rd_A	12673530	8441	0	0
sw_rst_ctrl_n_6_rd_A	12673530	8104	0	0
sw_rst_ctrl_n_7_rd_A	12673530	8403	0	0
sw_rst_regwen_0_rd_A	12673530	5819	0	0
sw_rst_regwen_1_rd_A	12673530	6093	0	0
sw_rst_regwen_2_rd_A	12673530	5782	0	0
sw_rst_regwen_3_rd_A	12673530	5795	0	0
sw_rst_regwen_4_rd_A	12673530	5954	0	0
sw_rst_regwen_5_rd_A	12673530	5985	0	0
sw_rst_regwen_6_rd_A	12673530	5532	0	0
sw_rst_regwen_7_rd_A	12673530	6080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	7490	0	0
T63	4204	504	0	0
T64	2840	114	0	0
T65	15188	549	0	0
T66	17888	1	0	0
T71	2579	2	0	0
T94	7925	240	0	0
T95	3665	38	0	0
T96	3062	57	0	0
T97	10347	373	0	0
T98	4415	15	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5461	0	0
T3	29131	21	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	252	0	0
T51	0	254	0	0
T80	0	87	0	0
T101	0	70	0	0
T103	0	81	0	0
T105	0	32	0	0
T130	0	88	0	0
T131	0	58	0	0
T132	0	274	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5392	0	0
T3	29131	43	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	281	0	0
T51	0	265	0	0
T80	0	57	0	0
T101	0	93	0	0
T103	0	55	0	0
T105	0	20	0	0
T130	0	95	0	0
T131	0	49	0	0
T132	0	272	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8218	0	0
T3	29131	14	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	52	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	41	0	0
T21	4037	0	0	0
T48	0	634	0	0
T87	0	44	0	0
T89	0	126	0	0
T92	0	9	0	0
T93	0	202	0	0
T101	0	66	0	0
T133	0	110	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8547	0	0
T3	29131	18	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	39	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	53	0	0
T21	4037	0	0	0
T48	0	570	0	0
T87	0	38	0	0
T89	0	138	0	0
T92	0	8	0	0
T93	0	219	0	0
T101	0	75	0	0
T133	0	104	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8386	0	0
T3	29131	20	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	47	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	56	0	0
T21	4037	0	0	0
T48	0	614	0	0
T87	0	49	0	0
T89	0	133	0	0
T92	0	7	0	0
T93	0	222	0	0
T101	0	68	0	0
T133	0	93	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8644	0	0
T3	29131	36	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	53	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	39	0	0
T21	4037	0	0	0
T48	0	642	0	0
T87	0	50	0	0
T89	0	138	0	0
T92	0	14	0	0
T93	0	166	0	0
T101	0	82	0	0
T133	0	111	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8416	0	0
T3	29131	38	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	63	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	56	0	0
T21	4037	0	0	0
T48	0	636	0	0
T51	0	500	0	0
T87	0	46	0	0
T89	0	134	0	0
T93	0	249	0	0
T101	0	76	0	0
T133	0	66	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8441	0	0
T3	29131	45	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	33	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	54	0	0
T21	4037	0	0	0
T48	0	618	0	0
T87	0	54	0	0
T89	0	137	0	0
T92	0	3	0	0
T93	0	192	0	0
T101	0	73	0	0
T133	0	136	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8104	0	0
T3	29131	17	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	50	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	22	0	0
T21	4037	0	0	0
T48	0	584	0	0
T87	0	47	0	0
T89	0	141	0	0
T92	0	7	0	0
T93	0	213	0	0
T101	0	98	0	0
T133	0	79	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	8403	0	0
T3	29131	21	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	46	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	26	0	0
T21	4037	0	0	0
T48	0	618	0	0
T87	0	28	0	0
T89	0	144	0	0
T92	0	6	0	0
T93	0	197	0	0
T101	0	97	0	0
T133	0	129	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5819	0	0
T3	29131	44	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	254	0	0
T51	0	298	0	0
T89	0	31	0	0
T93	0	41	0	0
T101	0	87	0	0
T103	0	67	0	0
T133	0	18	0	0
T134	0	7	0	0
T135	0	22	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	6093	0	0
T3	29131	37	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	193	0	0
T51	0	282	0	0
T89	0	34	0	0
T92	0	13	0	0
T93	0	36	0	0
T101	0	78	0	0
T103	0	87	0	0
T133	0	15	0	0
T134	0	9	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5782	0	0
T3	29131	31	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	222	0	0
T51	0	271	0	0
T89	0	50	0	0
T92	0	6	0	0
T93	0	30	0	0
T101	0	96	0	0
T103	0	79	0	0
T133	0	7	0	0
T134	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5795	0	0
T3	29131	34	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	235	0	0
T51	0	287	0	0
T89	0	35	0	0
T92	0	6	0	0
T93	0	38	0	0
T101	0	121	0	0
T103	0	87	0	0
T133	0	27	0	0
T134	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5954	0	0
T3	29131	16	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	253	0	0
T51	0	243	0	0
T89	0	16	0	0
T92	0	3	0	0
T93	0	25	0	0
T101	0	90	0	0
T103	0	65	0	0
T133	0	18	0	0
T134	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5985	0	0
T3	29131	35	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	245	0	0
T51	0	284	0	0
T89	0	30	0	0
T92	0	5	0	0
T93	0	31	0	0
T101	0	87	0	0
T103	0	99	0	0
T133	0	17	0	0
T134	0	9	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	5532	0	0
T3	29131	9	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	230	0	0
T51	0	293	0	0
T89	0	30	0	0
T92	0	6	0	0
T93	0	23	0	0
T101	0	86	0	0
T103	0	69	0	0
T133	0	36	0	0
T134	0	5	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12673530	6080	0	0
T3	29131	25	0	0
T4	2152	0	0	0
T5	5254	0	0	0
T6	3211	0	0	0
T7	4439	0	0	0
T8	26118	0	0	0
T9	3384	0	0	0
T10	28556	0	0	0
T11	5352	0	0	0
T21	4037	0	0	0
T48	0	234	0	0
T51	0	311	0	0
T89	0	19	0	0
T92	0	7	0	0
T93	0	20	0	0
T101	0	100	0	0
T103	0	69	0	0
T133	0	25	0	0
T134	0	3	0	0