Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	532384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

323505

1

T1

366

T2

887

T4

1054

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	452919	1			T1	523		T2	1324		T4	1598
values[0x0]	201493	1			T1	242		T2	575		T4	650
values[0x1]	201477	1			T1	235		T2	536		T4	662

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	447049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

408840

1

T1

465

T2

1124

T4

1350

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6028	1			T1	3		T4	3		T7	5
valid_sources[0x01]	3925	1			T1	3		T4	6		T7	8
valid_sources[0x02]	3239	1			T1	4		T4	2		T7	2
valid_sources[0x03]	3260	1			T1	7		T4	17		T7	8
valid_sources[0x04]	3013	1			T1	5		T4	68		T7	12
valid_sources[0x05]	2833	1			T1	6		T4	13		T7	6
valid_sources[0x06]	2893	1			T1	5		T4	16		T7	4
valid_sources[0x07]	2426	1			T1	2		T4	10		T7	6
valid_sources[0x08]	2604	1			T1	3		T7	9		T9	20
valid_sources[0x09]	2830	1			T1	6		T7	3		T9	1
valid_sources[0x0a]	2979	1			T1	4		T4	4		T7	13
valid_sources[0x0b]	2604	1			T1	10		T7	8		T9	11
valid_sources[0x0c]	3064	1			T1	3		T7	4		T9	19
valid_sources[0x0d]	2977	1			T1	1		T4	34		T7	17
valid_sources[0x0e]	2884	1			T1	3		T4	13		T7	4
valid_sources[0x0f]	2854	1			T1	1		T4	8		T7	10
valid_sources[0x10]	2990	1			T1	10		T4	20		T7	10
valid_sources[0x11]	2811	1			T1	3		T7	8		T9	21
valid_sources[0x12]	3511	1			T1	2		T2	10		T4	2
valid_sources[0x13]	3133	1			T1	1		T7	16		T9	2
valid_sources[0x14]	3385	1			T1	5		T7	9		T14	2
valid_sources[0x15]	3121	1			T1	3		T7	8		T9	3
valid_sources[0x16]	6433	1			T1	2		T7	6		T9	15
valid_sources[0x17]	6331	1			T1	4		T9	20		T11	1
valid_sources[0x18]	3177	1			T1	6		T7	5		T9	5
valid_sources[0x19]	3804	1			T4	15		T7	8		T9	16
valid_sources[0x1a]	3518	1			T1	1		T4	24		T7	4
valid_sources[0x1b]	4616	1			T1	4		T7	6		T9	6
valid_sources[0x1c]	3171	1			T1	4		T7	4		T9	1
valid_sources[0x1d]	3023	1			T1	8		T7	3		T9	1
valid_sources[0x1e]	2541	1			T1	1		T4	5		T7	6
valid_sources[0x1f]	2737	1			T1	1		T4	6		T7	8
valid_sources[0x20]	3406	1			T1	5		T4	7		T7	13
valid_sources[0x21]	3734	1			T1	4		T4	11		T7	5
valid_sources[0x22]	3074	1			T1	6		T4	19		T7	5
valid_sources[0x23]	3875	1			T1	3		T4	43		T7	4
valid_sources[0x24]	3080	1			T1	6		T7	8		T9	16
valid_sources[0x25]	2827	1			T1	5		T4	6		T7	21
valid_sources[0x26]	2573	1			T1	6		T4	14		T7	6
valid_sources[0x27]	3041	1			T1	5		T4	15		T7	16
valid_sources[0x28]	6944	1			T1	4		T4	7		T7	9
valid_sources[0x29]	2957	1			T1	3		T7	11		T9	19
valid_sources[0x2a]	4354	1			T1	5		T4	42		T7	11
valid_sources[0x2b]	2568	1			T1	7		T4	6		T7	4
valid_sources[0x2c]	2877	1			T1	1		T4	31		T7	6
valid_sources[0x2d]	3171	1			T1	10		T4	12		T7	6
valid_sources[0x2e]	3095	1			T1	4		T4	23		T7	5
valid_sources[0x2f]	3504	1			T1	3		T7	3		T9	10
valid_sources[0x30]	2971	1			T1	2		T7	14		T9	9
valid_sources[0x31]	2920	1			T1	3		T7	12		T9	11
valid_sources[0x32]	3888	1			T1	3		T2	269		T4	11
valid_sources[0x33]	4248	1			T1	2		T7	6		T9	2
valid_sources[0x34]	2736	1			T1	4		T4	59		T7	6
valid_sources[0x35]	3736	1			T1	5		T4	2		T7	7
valid_sources[0x36]	3403	1			T1	11		T4	24		T7	9
valid_sources[0x37]	2764	1			T1	6		T4	16		T7	9
valid_sources[0x38]	3759	1			T1	1		T7	11		T11	8
valid_sources[0x39]	3040	1			T1	3		T4	14		T7	4
valid_sources[0x3a]	3126	1			T1	3		T4	40		T7	14
valid_sources[0x3b]	3688	1			T1	4		T2	702		T4	3
valid_sources[0x3c]	3528	1			T1	4		T7	16		T9	7
valid_sources[0x3d]	2887	1			T1	4		T4	12		T7	13
valid_sources[0x3e]	3170	1			T1	7		T4	12		T7	5
valid_sources[0x3f]	3430	1			T1	7		T7	12		T9	7
valid_sources[0x40]	3584	1			T1	2		T7	14		T9	3
valid_sources[0x41]	3262	1			T1	4		T4	16		T7	8
valid_sources[0x42]	2667	1			T1	2		T4	41		T7	11
valid_sources[0x43]	3171	1			T1	12		T4	4		T7	15
valid_sources[0x44]	2733	1			T1	2		T2	193		T4	27
valid_sources[0x45]	3567	1			T1	4		T4	20		T7	10
valid_sources[0x46]	3682	1			T1	7		T7	5		T9	33
valid_sources[0x47]	3209	1			T1	2		T4	30		T7	10
valid_sources[0x48]	3882	1			T1	5		T2	240		T4	6
valid_sources[0x49]	2915	1			T1	6		T7	8		T9	10
valid_sources[0x4a]	3579	1			T1	3		T4	13		T7	4
valid_sources[0x4b]	3077	1			T1	8		T7	13		T9	2
valid_sources[0x4c]	2821	1			T1	5		T7	2		T9	16
valid_sources[0x4d]	2671	1			T1	2		T4	40		T7	2
valid_sources[0x4e]	3558	1			T1	3		T4	13		T7	15
valid_sources[0x4f]	3600	1			T1	5		T7	7		T9	1
valid_sources[0x50]	3731	1			T1	3		T4	63		T7	7
valid_sources[0x51]	2516	1			T1	3		T4	8		T7	8
valid_sources[0x52]	2999	1			T1	2		T4	16		T7	5
valid_sources[0x53]	2697	1			T1	1		T7	9		T9	5
valid_sources[0x54]	2764	1			T1	4		T7	7		T9	19
valid_sources[0x55]	2767	1			T7	6		T9	6		T11	5
valid_sources[0x56]	3039	1			T1	2		T4	21		T7	6
valid_sources[0x57]	3611	1			T1	4		T7	4		T9	19
valid_sources[0x58]	3036	1			T1	6		T4	22		T7	1
valid_sources[0x59]	2895	1			T1	5		T4	15		T7	6
valid_sources[0x5a]	2737	1			T1	3		T7	5		T9	13
valid_sources[0x5b]	3721	1			T1	5		T4	14		T7	9
valid_sources[0x5c]	3145	1			T1	4		T7	9		T9	8
valid_sources[0x5d]	2611	1			T1	1		T4	3		T7	7
valid_sources[0x5e]	3059	1			T1	2		T7	15		T9	2
valid_sources[0x5f]	2714	1			T4	13		T7	7		T9	16
valid_sources[0x60]	3670	1			T1	1		T4	35		T7	12
valid_sources[0x61]	4167	1			T1	4		T7	11		T9	5
valid_sources[0x62]	3073	1			T4	9		T7	2		T9	9
valid_sources[0x63]	2656	1			T1	4		T7	6		T9	34
valid_sources[0x64]	3119	1			T1	8		T2	3		T4	6
valid_sources[0x65]	3342	1			T1	4		T7	19		T9	1
valid_sources[0x66]	3347	1			T1	7		T7	19		T9	20
valid_sources[0x67]	3182	1			T1	2		T7	5		T14	2
valid_sources[0x68]	3397	1			T1	4		T7	9		T9	21
valid_sources[0x69]	2971	1			T1	5		T4	8		T7	8
valid_sources[0x6a]	2610	1			T1	4		T4	3		T7	11
valid_sources[0x6b]	3308	1			T1	2		T4	9		T7	7
valid_sources[0x6c]	3597	1			T1	9		T2	2		T4	18
valid_sources[0x6d]	3897	1			T1	8		T7	19		T9	4
valid_sources[0x6e]	2995	1			T1	3		T4	33		T7	5
valid_sources[0x6f]	3008	1			T1	5		T4	12		T7	18
valid_sources[0x70]	3115	1			T1	4		T4	26		T7	5
valid_sources[0x71]	3009	1			T1	4		T4	13		T7	8
valid_sources[0x72]	3834	1			T1	2		T4	12		T7	8
valid_sources[0x73]	3020	1			T1	7		T4	39		T7	5
valid_sources[0x74]	3812	1			T1	1		T4	32		T7	9
valid_sources[0x75]	3859	1			T1	4		T7	5		T9	5
valid_sources[0x76]	2875	1			T1	2		T4	69		T7	14
valid_sources[0x77]	2940	1			T1	4		T7	5		T9	8
valid_sources[0x78]	3194	1			T1	4		T7	3		T9	2
valid_sources[0x79]	3139	1			T1	4		T4	61		T7	9
valid_sources[0x7a]	2489	1			T1	1		T4	20		T7	10
valid_sources[0x7b]	3484	1			T1	8		T4	28		T7	1
valid_sources[0x7c]	2953	1			T1	3		T7	7		T9	13
valid_sources[0x7d]	3099	1			T1	7		T4	18		T7	8
valid_sources[0x7e]	3077	1			T1	7		T4	35		T7	7
valid_sources[0x7f]	2761	1			T1	1		T4	9		T7	17
valid_sources[0x80]	5667	1			T1	3		T7	11		T9	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

212597

1

T1

253

T2

600

T4

719

values[0x0]

all_enables

biggest_size

71723

1

T1

77

T2

194

T4

228

values[0x1]

all_enables

biggest_size

39185

1

T1

36

T2

93

T4

107