Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T4,T7

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	42943913	7191	0	0
CascadeEffAonToRstPorAboveRise_A	42943913	7191	0	0
CascadeEffAonToRstPorIoAboveFall_A	41224818	7191	0	0
CascadeEffAonToRstPorIoAboveRise_A	41224818	7191	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	20613079	7191	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	20613079	7191	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	10306153	7191	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	10306153	7191	0	0
CascadeEffAonToRstPorUcbAboveFall_A	20612913	7191	0	0
CascadeEffAonToRstPorUcbAboveRise_A	20612913	7191	0	0
CascadeLcToLcAboveFall_A	42943913	18514	0	0
CascadeLcToLcAboveRise_A	42943913	18514	0	0
CascadeLcToLcAonAboveFall_A	1301864	18514	0	0
CascadeLcToLcAonAboveRise_A	1301864	18514	0	0
CascadeLcToLcShadowedAboveFall_A	42943913	18514	0	0
CascadeLcToLcShadowedAboveRise_A	42943913	18514	0	0
CascadePorToAonAboveFall_A	1301864	5766	0	0
CascadeSysToSysAboveFall_A	42943913	18514	0	0
CascadeSysToSysAboveRise_A	42943913	18514	0	0
ScanRstToAonRise_A	1301864	202	0	0
StablePorToAonRise_A	1301864	7191	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	9113070	18514	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	9113070	18514	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	9113070	18514	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	9113070	18514	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	10306153	18514	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	10306153	18514	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	9113070	18514	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	9113070	18514	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	9113070	18514	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	9113070	18514	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	7191	0	0
T1	34635	1	0	0
T2	74992	14	0	0
T3	24312	8	0	0
T4	148010	17	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	13	0	0
T8	19078	2	0	0
T9	175241	20	0	0
T10	24285	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	7191	0	0
T1	34635	1	0	0
T2	74992	14	0	0
T3	24312	8	0	0
T4	148010	17	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	13	0	0
T8	19078	2	0	0
T9	175241	20	0	0
T10	24285	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41224818	7191	0	0
T1	33248	1	0	0
T2	71984	14	0	0
T3	23339	8	0	0
T4	142063	17	0	0
T5	15094	2	0	0
T6	9081	2	0	0
T7	111277	13	0	0
T8	18310	2	0	0
T9	168225	20	0	0
T10	23329	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41224818	7191	0	0
T1	33248	1	0	0
T2	71984	14	0	0
T3	23339	8	0	0
T4	142063	17	0	0
T5	15094	2	0	0
T6	9081	2	0	0
T7	111277	13	0	0
T8	18310	2	0	0
T9	168225	20	0	0
T10	23329	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20613079	7191	0	0
T1	16624	1	0	0
T2	36000	14	0	0
T3	11663	8	0	0
T4	71039	17	0	0
T5	7545	2	0	0
T6	4540	2	0	0
T7	55644	13	0	0
T8	9159	2	0	0
T9	84117	20	0	0
T10	11660	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20613079	7191	0	0
T1	16624	1	0	0
T2	36000	14	0	0
T3	11663	8	0	0
T4	71039	17	0	0
T5	7545	2	0	0
T6	4540	2	0	0
T7	55644	13	0	0
T8	9159	2	0	0
T9	84117	20	0	0
T10	11660	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	7191	0	0
T1	8312	1	0	0
T2	17997	14	0	0
T3	5835	8	0	0
T4	35519	17	0	0
T5	3772	2	0	0
T6	2269	2	0	0
T7	27819	13	0	0
T8	4576	2	0	0
T9	42055	20	0	0
T10	5833	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	7191	0	0
T1	8312	1	0	0
T2	17997	14	0	0
T3	5835	8	0	0
T4	35519	17	0	0
T5	3772	2	0	0
T6	2269	2	0	0
T7	27819	13	0	0
T8	4576	2	0	0
T9	42055	20	0	0
T10	5833	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20612913	7191	0	0
T1	16623	1	0	0
T2	35988	14	0	0
T3	11671	8	0	0
T4	71035	17	0	0
T5	7546	2	0	0
T6	4540	2	0	0
T7	55636	13	0	0
T8	9154	2	0	0
T9	84123	20	0	0
T10	11655	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20612913	7191	0	0
T1	16623	1	0	0
T2	35988	14	0	0
T3	11671	8	0	0
T4	71035	17	0	0
T5	7546	2	0	0
T6	4540	2	0	0
T7	55636	13	0	0
T8	9154	2	0	0
T9	84123	20	0	0
T10	11655	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	18514	0	0
T1	34635	1	0	0
T2	74992	50	0	0
T3	24312	8	0	0
T4	148010	59	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	45	0	0
T8	19078	6	0	0
T9	175241	50	0	0
T10	24285	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	18514	0	0
T1	34635	1	0	0
T2	74992	50	0	0
T3	24312	8	0	0
T4	148010	59	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	45	0	0
T8	19078	6	0	0
T9	175241	50	0	0
T10	24285	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	18514	0	0
T1	1037	1	0	0
T2	2323	50	0	0
T3	731	8	0	0
T4	4528	59	0	0
T5	471	2	0	0
T6	282	2	0	0
T7	3519	45	0	0
T8	570	6	0	0
T9	5306	50	0	0
T10	730	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	18514	0	0
T1	1037	1	0	0
T2	2323	50	0	0
T3	731	8	0	0
T4	4528	59	0	0
T5	471	2	0	0
T6	282	2	0	0
T7	3519	45	0	0
T8	570	6	0	0
T9	5306	50	0	0
T10	730	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	18514	0	0
T1	34635	1	0	0
T2	74992	50	0	0
T3	24312	8	0	0
T4	148010	59	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	45	0	0
T8	19078	6	0	0
T9	175241	50	0	0
T10	24285	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	18514	0	0
T1	34635	1	0	0
T2	74992	50	0	0
T3	24312	8	0	0
T4	148010	59	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	45	0	0
T8	19078	6	0	0
T9	175241	50	0	0
T10	24285	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	5766	0	0
T1	1037	1	0	0
T2	2323	6	0	0
T3	731	8	0	0
T4	4528	8	0	0
T5	471	11	0	0
T6	282	4	0	0
T7	3519	8	0	0
T8	570	1	0	0
T9	5306	10	0	0
T10	730	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	18514	0	0
T1	34635	1	0	0
T2	74992	50	0	0
T3	24312	8	0	0
T4	148010	59	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	45	0	0
T8	19078	6	0	0
T9	175241	50	0	0
T10	24285	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42943913	18514	0	0
T1	34635	1	0	0
T2	74992	50	0	0
T3	24312	8	0	0
T4	148010	59	0	0
T5	15723	2	0	0
T6	9459	2	0	0
T7	115919	45	0	0
T8	19078	6	0	0
T9	175241	50	0	0
T10	24285	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	202	0	0
T2	2323	1	0	0
T3	731	0	0	0
T4	4528	1	0	0
T5	471	0	0	0
T6	282	0	0	0
T7	3519	0	0	0
T8	570	0	0	0
T9	5306	2	0	0
T10	730	0	0	0
T11	1261	0	0	0
T26	0	4	0	0
T39	0	4	0	0
T50	0	8	0	0
T57	0	1	0	0
T60	0	6	0	0
T87	0	2	0	0
T95	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	7191	0	0
T1	1037	1	0	0
T2	2323	14	0	0
T3	731	8	0	0
T4	4528	17	0	0
T5	471	2	0	0
T6	282	2	0	0
T7	3519	13	0	0
T8	570	2	0	0
T9	5306	20	0	0
T10	730	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	18514	0	0
T1	8312	1	0	0
T2	17997	50	0	0
T3	5835	8	0	0
T4	35519	59	0	0
T5	3772	2	0	0
T6	2269	2	0	0
T7	27819	45	0	0
T8	4576	6	0	0
T9	42055	50	0	0
T10	5833	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	18514	0	0
T1	8312	1	0	0
T2	17997	50	0	0
T3	5835	8	0	0
T4	35519	59	0	0
T5	3772	2	0	0
T6	2269	2	0	0
T7	27819	45	0	0
T8	4576	6	0	0
T9	42055	50	0	0
T10	5833	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9113070	18514	0	0
T1	8221	1	0	0
T2	13527	50	0	0
T3	5481	8	0	0
T4	30275	59	0	0
T5	3658	2	0	0
T6	2227	2	0	0
T7	23312	45	0	0
T8	4335	6	0	0
T9	36766	50	0	0
T10	5285	8	0	0