Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T25
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T14
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T26
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T26
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T26
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T13
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	10306153	12115	0	0
gen_assertions[0].RstEnOn_A	10306153	970	0	0
gen_assertions[0].RstNOff_A	10306153	12115	0	0
gen_assertions[0].RstNOn_A	10306153	970	0	0
gen_assertions[1].RstEnOff_A	41224818	11017	0	0
gen_assertions[1].RstEnOn_A	41224818	915	0	0
gen_assertions[1].RstNOff_A	41224818	11017	0	0
gen_assertions[1].RstNOn_A	41224818	915	0	0
gen_assertions[2].RstEnOff_A	20613079	11096	0	0
gen_assertions[2].RstEnOn_A	20613079	934	0	0
gen_assertions[2].RstNOff_A	20613079	11096	0	0
gen_assertions[2].RstNOn_A	20613079	934	0	0
gen_assertions[3].RstEnOff_A	20612913	11116	0	0
gen_assertions[3].RstEnOn_A	20612913	953	0	0
gen_assertions[3].RstNOff_A	20612913	11116	0	0
gen_assertions[3].RstNOn_A	20612913	953	0	0
gen_assertions[4].RstEnOff_A	1301864	18285	0	0
gen_assertions[4].RstEnOn_A	1301864	1011	0	0
gen_assertions[4].RstNOff_A	1301864	18285	0	0
gen_assertions[4].RstNOn_A	1301864	1011	0	0
gen_assertions[5].RstEnOff_A	10306153	12325	0	0
gen_assertions[5].RstEnOn_A	10306153	1033	0	0
gen_assertions[5].RstNOff_A	10306153	12325	0	0
gen_assertions[5].RstNOn_A	10306153	1033	0	0
gen_assertions[6].RstEnOff_A	10306153	12388	0	0
gen_assertions[6].RstEnOn_A	10306153	1089	0	0
gen_assertions[6].RstNOff_A	10306153	12388	0	0
gen_assertions[6].RstNOn_A	10306153	1089	0	0
gen_assertions[7].RstEnOff_A	10306153	12448	0	0
gen_assertions[7].RstEnOn_A	10306153	1162	0	0
gen_assertions[7].RstNOff_A	10306153	12448	0	0
gen_assertions[7].RstNOn_A	10306153	1162	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12115	0	0
T1	8312	7	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	970	0	0
T1	8312	7	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	5	0	0
T25	0	1	0	0
T26	0	8	0	0
T38	0	1	0	0
T50	0	5	0	0
T59	0	4	0	0
T60	0	44	0	0
T86	0	5	0	0
T87	0	27	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12115	0	0
T1	8312	7	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	970	0	0
T1	8312	7	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	5	0	0
T25	0	1	0	0
T26	0	8	0	0
T38	0	1	0	0
T50	0	5	0	0
T59	0	4	0	0
T60	0	44	0	0
T86	0	5	0	0
T87	0	27	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41224818	11017	0	0
T1	33248	7	0	0
T2	71984	35	0	0
T3	23339	0	0	0
T4	142063	42	0	0
T5	15094	0	0	0
T6	9081	0	0	0
T7	111277	31	0	0
T8	18310	3	0	0
T9	168225	27	0	0
T10	23329	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	5	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41224818	915	0	0
T1	33248	7	0	0
T2	71984	0	0	0
T3	23339	0	0	0
T4	142063	0	0	0
T5	15094	0	0	0
T6	9081	0	0	0
T7	111277	0	0	0
T8	18310	0	0	0
T9	168225	0	0	0
T10	23329	0	0	0
T11	0	5	0	0
T14	0	1	0	0
T26	0	7	0	0
T50	0	7	0	0
T59	0	3	0	0
T60	0	51	0	0
T62	0	2	0	0
T86	0	3	0	0
T87	0	30	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41224818	11017	0	0
T1	33248	7	0	0
T2	71984	35	0	0
T3	23339	0	0	0
T4	142063	42	0	0
T5	15094	0	0	0
T6	9081	0	0	0
T7	111277	31	0	0
T8	18310	3	0	0
T9	168225	27	0	0
T10	23329	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	5	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41224818	915	0	0
T1	33248	7	0	0
T2	71984	0	0	0
T3	23339	0	0	0
T4	142063	0	0	0
T5	15094	0	0	0
T6	9081	0	0	0
T7	111277	0	0	0
T8	18310	0	0	0
T9	168225	0	0	0
T10	23329	0	0	0
T11	0	5	0	0
T14	0	1	0	0
T26	0	7	0	0
T50	0	7	0	0
T59	0	3	0	0
T60	0	51	0	0
T62	0	2	0	0
T86	0	3	0	0
T87	0	30	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20613079	11096	0	0
T1	16624	7	0	0
T2	36000	35	0	0
T3	11663	0	0	0
T4	71039	42	0	0
T5	7545	0	0	0
T6	4540	0	0	0
T7	55644	31	0	0
T8	9159	3	0	0
T9	84117	27	0	0
T10	11660	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	5	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20613079	934	0	0
T1	16624	7	0	0
T2	36000	0	0	0
T3	11663	0	0	0
T4	71039	0	0	0
T5	7545	0	0	0
T6	4540	0	0	0
T7	55644	0	0	0
T8	9159	0	0	0
T9	84117	0	0	0
T10	11660	0	0	0
T11	0	9	0	0
T13	0	1	0	0
T14	0	1	0	0
T26	0	9	0	0
T50	0	6	0	0
T59	0	6	0	0
T60	0	52	0	0
T62	0	2	0	0
T87	0	32	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20613079	11096	0	0
T1	16624	7	0	0
T2	36000	35	0	0
T3	11663	0	0	0
T4	71039	42	0	0
T5	7545	0	0	0
T6	4540	0	0	0
T7	55644	31	0	0
T8	9159	3	0	0
T9	84117	27	0	0
T10	11660	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	5	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20613079	934	0	0
T1	16624	7	0	0
T2	36000	0	0	0
T3	11663	0	0	0
T4	71039	0	0	0
T5	7545	0	0	0
T6	4540	0	0	0
T7	55644	0	0	0
T8	9159	0	0	0
T9	84117	0	0	0
T10	11660	0	0	0
T11	0	9	0	0
T13	0	1	0	0
T14	0	1	0	0
T26	0	9	0	0
T50	0	6	0	0
T59	0	6	0	0
T60	0	52	0	0
T62	0	2	0	0
T87	0	32	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20612913	11116	0	0
T1	16623	10	0	0
T2	35988	35	0	0
T3	11671	0	0	0
T4	71035	42	0	0
T5	7546	0	0	0
T6	4540	0	0	0
T7	55636	31	0	0
T8	9154	3	0	0
T9	84123	27	0	0
T10	11655	0	0	0
T11	0	8	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20612913	953	0	0
T1	16623	10	0	0
T2	35988	0	0	0
T3	11671	0	0	0
T4	71035	0	0	0
T5	7546	0	0	0
T6	4540	0	0	0
T7	55636	0	0	0
T8	9154	0	0	0
T9	84123	0	0	0
T10	11655	0	0	0
T11	0	8	0	0
T13	0	1	0	0
T26	0	8	0	0
T38	0	1	0	0
T50	0	8	0	0
T59	0	5	0	0
T60	0	49	0	0
T62	0	3	0	0
T87	0	24	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20612913	11116	0	0
T1	16623	10	0	0
T2	35988	35	0	0
T3	11671	0	0	0
T4	71035	42	0	0
T5	7546	0	0	0
T6	4540	0	0	0
T7	55636	31	0	0
T8	9154	3	0	0
T9	84123	27	0	0
T10	11655	0	0	0
T11	0	8	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20612913	953	0	0
T1	16623	10	0	0
T2	35988	0	0	0
T3	11671	0	0	0
T4	71035	0	0	0
T5	7546	0	0	0
T6	4540	0	0	0
T7	55636	0	0	0
T8	9154	0	0	0
T9	84123	0	0	0
T10	11655	0	0	0
T11	0	8	0	0
T13	0	1	0	0
T26	0	8	0	0
T38	0	1	0	0
T50	0	8	0	0
T59	0	5	0	0
T60	0	49	0	0
T62	0	3	0	0
T87	0	24	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	18285	0	0
T1	1037	9	0	0
T2	2323	50	0	0
T3	731	3	0	0
T4	4528	59	0	0
T5	471	2	0	0
T6	282	2	0	0
T7	3519	45	0	0
T8	570	6	0	0
T9	5306	50	0	0
T10	730	3	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	1011	0	0
T1	1037	8	0	0
T2	2323	0	0	0
T3	731	0	0	0
T4	4528	0	0	0
T5	471	0	0	0
T6	282	0	0	0
T7	3519	0	0	0
T8	570	0	0	0
T9	5306	0	0	0
T10	730	0	0	0
T11	0	11	0	0
T26	0	9	0	0
T39	0	15	0	0
T50	0	4	0	0
T59	0	8	0	0
T60	0	46	0	0
T62	0	5	0	0
T68	0	1	0	0
T87	0	29	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	18285	0	0
T1	1037	9	0	0
T2	2323	50	0	0
T3	731	3	0	0
T4	4528	59	0	0
T5	471	2	0	0
T6	282	2	0	0
T7	3519	45	0	0
T8	570	6	0	0
T9	5306	50	0	0
T10	730	3	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1301864	1011	0	0
T1	1037	8	0	0
T2	2323	0	0	0
T3	731	0	0	0
T4	4528	0	0	0
T5	471	0	0	0
T6	282	0	0	0
T7	3519	0	0	0
T8	570	0	0	0
T9	5306	0	0	0
T10	730	0	0	0
T11	0	11	0	0
T26	0	9	0	0
T39	0	15	0	0
T50	0	4	0	0
T59	0	8	0	0
T60	0	46	0	0
T62	0	5	0	0
T68	0	1	0	0
T87	0	29	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12325	0	0
T1	8312	11	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	10	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	1033	0	0
T1	8312	11	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	10	0	0
T26	0	10	0	0
T38	0	1	0	0
T39	0	12	0	0
T50	0	5	0	0
T59	0	9	0	0
T60	0	47	0	0
T62	0	5	0	0
T87	0	25	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12325	0	0
T1	8312	11	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	10	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	1033	0	0
T1	8312	11	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	10	0	0
T26	0	10	0	0
T38	0	1	0	0
T39	0	12	0	0
T50	0	5	0	0
T59	0	9	0	0
T60	0	47	0	0
T62	0	5	0	0
T87	0	25	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12388	0	0
T1	8312	11	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	11	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	1089	0	0
T1	8312	11	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	11	0	0
T26	0	8	0	0
T39	0	13	0	0
T44	0	1	0	0
T50	0	6	0	0
T59	0	8	0	0
T60	0	45	0	0
T62	0	6	0	0
T87	0	24	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12388	0	0
T1	8312	11	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	11	0	0
T12	0	4	0	0
T13	0	4	0	0
T14	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	1089	0	0
T1	8312	11	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	11	0	0
T26	0	8	0	0
T39	0	13	0	0
T44	0	1	0	0
T50	0	6	0	0
T59	0	8	0	0
T60	0	45	0	0
T62	0	6	0	0
T87	0	24	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12448	0	0
T1	8312	12	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	5	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	1162	0	0
T1	8312	12	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	9	0	0
T13	0	1	0	0
T14	0	1	0	0
T26	0	9	0	0
T50	0	8	0	0
T59	0	10	0	0
T60	0	49	0	0
T62	0	7	0	0
T87	0	26	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	12448	0	0
T1	8312	12	0	0
T2	17997	36	0	0
T3	5835	0	0	0
T4	35519	42	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	32	0	0
T8	4576	4	0	0
T9	42055	30	0	0
T10	5833	0	0	0
T11	0	9	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	5	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10306153	1162	0	0
T1	8312	12	0	0
T2	17997	0	0	0
T3	5835	0	0	0
T4	35519	0	0	0
T5	3772	0	0	0
T6	2269	0	0	0
T7	27819	0	0	0
T8	4576	0	0	0
T9	42055	0	0	0
T10	5833	0	0	0
T11	0	9	0	0
T13	0	1	0	0
T14	0	1	0	0
T26	0	9	0	0
T50	0	8	0	0
T59	0	10	0	0
T60	0	49	0	0
T62	0	7	0	0
T87	0	26	0	0