Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	9930448	8705	0	0
alert_regwen_rd_A	9930448	2760	0	0
cpu_regwen_rd_A	9930448	2854	0	0
sw_rst_ctrl_n_0_rd_A	9930448	5635	0	0
sw_rst_ctrl_n_1_rd_A	9930448	5671	0	0
sw_rst_ctrl_n_2_rd_A	9930448	5619	0	0
sw_rst_ctrl_n_3_rd_A	9930448	5583	0	0
sw_rst_ctrl_n_4_rd_A	9930448	5427	0	0
sw_rst_ctrl_n_5_rd_A	9930448	5420	0	0
sw_rst_ctrl_n_6_rd_A	9930448	5578	0	0
sw_rst_ctrl_n_7_rd_A	9930448	5535	0	0
sw_rst_regwen_0_rd_A	9930448	3378	0	0
sw_rst_regwen_1_rd_A	9930448	3228	0	0
sw_rst_regwen_2_rd_A	9930448	3373	0	0
sw_rst_regwen_3_rd_A	9930448	3316	0	0
sw_rst_regwen_4_rd_A	9930448	3241	0	0
sw_rst_regwen_5_rd_A	9930448	3464	0	0
sw_rst_regwen_6_rd_A	9930448	3214	0	0
sw_rst_regwen_7_rd_A	9930448	3288	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	8705	0	0
T64	19820	3	0	0
T65	4705	24	0	0
T69	7138	375	0	0
T70	3855	41	0	0
T71	17864	2	0	0
T72	11675	737	0	0
T88	2827	9	0	0
T89	7644	305	0	0
T90	4706	20	0	0
T91	2888	291	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	2760	0	0
T9	36766	71	0	0
T10	5285	0	0	0
T11	10058	0	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	0	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T83	0	79	0	0
T99	0	15	0	0
T119	0	262	0	0
T120	0	61	0	0
T121	0	100	0	0
T122	0	11	0	0
T123	0	58	0	0
T124	0	148	0	0
T125	0	33	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	2854	0	0
T9	36766	53	0	0
T10	5285	0	0	0
T11	10058	0	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	0	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T83	0	75	0	0
T99	0	24	0	0
T119	0	237	0	0
T120	0	68	0	0
T121	0	91	0	0
T122	0	53	0	0
T123	0	48	0	0
T124	0	144	0	0
T125	0	65	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5635	0	0
T9	36766	63	0	0
T10	5285	0	0	0
T11	10058	83	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	3	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	63	0	0
T68	0	5	0	0
T82	0	2	0	0
T83	0	81	0	0
T126	0	153	0	0
T127	0	3	0	0
T128	0	213	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5671	0	0
T9	36766	82	0	0
T10	5285	0	0	0
T11	10058	98	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	10	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	6	0	0
T26	77027	0	0	0
T62	0	66	0	0
T68	0	3	0	0
T82	0	18	0	0
T126	0	167	0	0
T127	0	7	0	0
T128	0	277	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5619	0	0
T9	36766	60	0	0
T10	5285	0	0	0
T11	10058	62	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	0	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	8	0	0
T26	77027	0	0	0
T62	0	69	0	0
T82	0	17	0	0
T83	0	51	0	0
T126	0	161	0	0
T127	0	12	0	0
T128	0	183	0	0
T129	0	134	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5583	0	0
T9	36766	85	0	0
T10	5285	0	0	0
T11	10058	91	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	13	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	9	0	0
T26	77027	0	0	0
T62	0	76	0	0
T68	0	6	0	0
T82	0	9	0	0
T126	0	179	0	0
T127	0	7	0	0
T128	0	184	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5427	0	0
T9	36766	71	0	0
T10	5285	0	0	0
T11	10058	115	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	13	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	4	0	0
T26	77027	0	0	0
T62	0	82	0	0
T68	0	13	0	0
T82	0	22	0	0
T126	0	173	0	0
T127	0	1	0	0
T128	0	220	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5420	0	0
T9	36766	79	0	0
T10	5285	0	0	0
T11	10058	94	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	11	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	67	0	0
T68	0	9	0	0
T82	0	16	0	0
T83	0	88	0	0
T126	0	129	0	0
T127	0	8	0	0
T128	0	184	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5578	0	0
T9	36766	68	0	0
T10	5285	0	0	0
T11	10058	108	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	7	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	6	0	0
T26	77027	0	0	0
T62	0	55	0	0
T68	0	10	0	0
T82	0	13	0	0
T126	0	152	0	0
T127	0	7	0	0
T128	0	201	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	5535	0	0
T9	36766	65	0	0
T10	5285	0	0	0
T11	10058	89	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	9	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	12	0	0
T26	77027	0	0	0
T62	0	72	0	0
T68	0	11	0	0
T82	0	21	0	0
T126	0	155	0	0
T127	0	2	0	0
T128	0	129	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3378	0	0
T9	36766	80	0	0
T10	5285	0	0	0
T11	10058	37	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	0	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	34	0	0
T68	0	2	0	0
T82	0	12	0	0
T83	0	67	0	0
T126	0	37	0	0
T127	0	3	0	0
T128	0	35	0	0
T129	0	8	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3228	0	0
T9	36766	92	0	0
T10	5285	0	0	0
T11	10058	28	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	0	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	20	0	0
T82	0	8	0	0
T83	0	84	0	0
T99	0	33	0	0
T126	0	27	0	0
T127	0	15	0	0
T128	0	32	0	0
T129	0	21	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3373	0	0
T9	36766	74	0	0
T10	5285	0	0	0
T11	10058	21	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	2	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	25	0	0
T68	0	7	0	0
T82	0	5	0	0
T83	0	60	0	0
T126	0	31	0	0
T127	0	2	0	0
T128	0	43	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3316	0	0
T9	36766	61	0	0
T10	5285	0	0	0
T11	10058	26	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	2	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	27	0	0
T68	0	6	0	0
T82	0	5	0	0
T83	0	93	0	0
T126	0	37	0	0
T127	0	1	0	0
T128	0	20	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3241	0	0
T9	36766	85	0	0
T10	5285	0	0	0
T11	10058	21	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	7	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	25	0	0
T68	0	3	0	0
T82	0	5	0	0
T83	0	68	0	0
T126	0	18	0	0
T127	0	11	0	0
T128	0	45	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3464	0	0
T9	36766	74	0	0
T10	5285	0	0	0
T11	10058	14	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	8	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	32	0	0
T68	0	10	0	0
T82	0	15	0	0
T83	0	73	0	0
T126	0	44	0	0
T127	0	4	0	0
T128	0	26	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3214	0	0
T9	36766	71	0	0
T10	5285	0	0	0
T11	10058	24	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	6	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	23	0	0
T68	0	3	0	0
T82	0	10	0	0
T83	0	62	0	0
T126	0	15	0	0
T127	0	7	0	0
T128	0	46	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9930448	3288	0	0
T9	36766	79	0	0
T10	5285	0	0	0
T11	10058	26	0	0
T12	4028	0	0	0
T13	2797	0	0	0
T14	5322	1	0	0
T23	2380	0	0	0
T24	5103	0	0	0
T25	1899	0	0	0
T26	77027	0	0	0
T62	0	20	0	0
T68	0	2	0	0
T82	0	8	0	0
T83	0	80	0	0
T126	0	29	0	0
T127	0	5	0	0
T128	0	35	0	0