Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	636360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

382410

1

T1

1188

T2

74

T3

968

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	543355	1			T1	1845		T2	99		T3	1489
values[0x0]	237433	1			T1	645		T2	60		T3	621
values[0x1]	237982	1			T1	643		T2	53		T3	600

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	534099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

484671

1

T1

1497

T2

95

T3

1255

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3162	1			T1	4		T3	13		T4	3
valid_sources[0x01]	4043	1			T1	11		T3	12		T7	2
valid_sources[0x02]	3540	1			T1	9		T3	10		T9	2
valid_sources[0x03]	6035	1			T1	27		T3	11		T4	12
valid_sources[0x04]	3546	1			T1	37		T3	9		T4	8
valid_sources[0x05]	3497	1			T1	30		T3	10		T4	2
valid_sources[0x06]	3705	1			T1	1		T3	9		T4	4
valid_sources[0x07]	3209	1			T2	26		T3	16		T4	1
valid_sources[0x08]	6332	1			T1	6		T3	14		T4	6
valid_sources[0x09]	3935	1			T1	8		T3	7		T11	108
valid_sources[0x0a]	3627	1			T1	4		T3	7		T4	7
valid_sources[0x0b]	3340	1			T1	19		T3	9		T4	2
valid_sources[0x0c]	4192	1			T1	6		T3	16		T4	1
valid_sources[0x0d]	3565	1			T1	23		T3	7		T4	2
valid_sources[0x0e]	6745	1			T1	19		T3	11		T4	7
valid_sources[0x0f]	3344	1			T1	4		T3	13		T4	4
valid_sources[0x10]	6558	1			T1	24		T3	8		T4	15
valid_sources[0x11]	3484	1			T1	14		T3	13		T4	3
valid_sources[0x12]	4694	1			T1	11		T3	8		T4	9
valid_sources[0x13]	4191	1			T1	1		T3	12		T7	1
valid_sources[0x14]	3197	1			T1	24		T3	12		T4	2
valid_sources[0x15]	3363	1			T1	8		T3	12		T9	155
valid_sources[0x16]	3364	1			T1	21		T3	18		T4	4
valid_sources[0x17]	3350	1			T1	3		T3	17		T4	14
valid_sources[0x18]	3581	1			T3	13		T4	1		T7	1
valid_sources[0x19]	2896	1			T1	7		T3	16		T7	1
valid_sources[0x1a]	3358	1			T1	3		T3	11		T4	11
valid_sources[0x1b]	3540	1			T2	5		T3	15		T7	1
valid_sources[0x1c]	4028	1			T1	10		T3	17		T4	1
valid_sources[0x1d]	6858	1			T1	5		T3	9		T4	2
valid_sources[0x1e]	3643	1			T1	23		T3	14		T4	3
valid_sources[0x1f]	4799	1			T1	21		T3	11		T4	1
valid_sources[0x20]	3516	1			T1	39		T3	9		T9	113
valid_sources[0x21]	3383	1			T1	8		T3	12		T4	3
valid_sources[0x22]	3225	1			T1	22		T3	7		T4	2
valid_sources[0x23]	3135	1			T1	31		T3	13		T4	2
valid_sources[0x24]	2976	1			T1	3		T3	6		T4	2
valid_sources[0x25]	5249	1			T1	12		T3	14		T7	4
valid_sources[0x26]	3770	1			T1	16		T3	13		T4	10
valid_sources[0x27]	3631	1			T1	21		T3	6		T4	4
valid_sources[0x28]	3491	1			T1	18		T3	11		T4	4
valid_sources[0x29]	3612	1			T1	27		T2	20		T3	16
valid_sources[0x2a]	5220	1			T1	1		T3	9		T9	63
valid_sources[0x2b]	3767	1			T1	9		T3	13		T4	1
valid_sources[0x2c]	2863	1			T3	7		T7	4		T11	77
valid_sources[0x2d]	4143	1			T1	9		T3	10		T7	6
valid_sources[0x2e]	3304	1			T1	24		T3	11		T4	1
valid_sources[0x2f]	3426	1			T1	5		T3	17		T7	3
valid_sources[0x30]	3857	1			T1	13		T3	17		T4	4
valid_sources[0x31]	3764	1			T1	26		T3	11		T7	2
valid_sources[0x32]	3776	1			T3	12		T7	2		T11	69
valid_sources[0x33]	3952	1			T1	5		T3	14		T4	1
valid_sources[0x34]	7378	1			T1	12		T3	11		T4	1
valid_sources[0x35]	3479	1			T1	20		T3	9		T11	64
valid_sources[0x36]	3389	1			T1	10		T3	11		T7	1
valid_sources[0x37]	3120	1			T1	10		T2	13		T3	11
valid_sources[0x38]	3800	1			T1	4		T3	10		T7	2
valid_sources[0x39]	3697	1			T1	15		T3	7		T7	2
valid_sources[0x3a]	4580	1			T3	9		T4	3		T7	3
valid_sources[0x3b]	3327	1			T1	10		T3	12		T4	4
valid_sources[0x3c]	3750	1			T1	20		T3	6		T9	6
valid_sources[0x3d]	3539	1			T1	17		T3	4		T9	309
valid_sources[0x3e]	3684	1			T1	11		T3	16		T4	5
valid_sources[0x3f]	4072	1			T1	15		T3	3		T4	3
valid_sources[0x40]	3588	1			T1	5		T3	8		T11	115
valid_sources[0x41]	4082	1			T1	61		T3	8		T4	5
valid_sources[0x42]	3474	1			T1	12		T3	12		T7	2
valid_sources[0x43]	3520	1			T1	18		T3	8		T7	1
valid_sources[0x44]	6696	1			T1	5		T3	5		T4	4
valid_sources[0x45]	4132	1			T1	17		T3	17		T4	2
valid_sources[0x46]	3112	1			T3	17		T4	7		T7	1
valid_sources[0x47]	3931	1			T1	46		T3	9		T4	1
valid_sources[0x48]	3426	1			T1	15		T3	10		T4	17
valid_sources[0x49]	6582	1			T3	15		T7	2		T11	100
valid_sources[0x4a]	3933	1			T1	29		T3	13		T7	1
valid_sources[0x4b]	4436	1			T1	28		T3	11		T11	91
valid_sources[0x4c]	4098	1			T1	12		T3	3		T4	3
valid_sources[0x4d]	3021	1			T1	6		T3	14		T4	1
valid_sources[0x4e]	3445	1			T1	18		T3	20		T11	94
valid_sources[0x4f]	4243	1			T1	5		T3	17		T4	13
valid_sources[0x50]	5114	1			T1	44		T3	6		T4	4
valid_sources[0x51]	4580	1			T1	42		T3	12		T11	110
valid_sources[0x52]	3150	1			T3	11		T4	4		T7	1
valid_sources[0x53]	3249	1			T1	9		T3	11		T4	9
valid_sources[0x54]	4020	1			T1	16		T3	3		T4	1
valid_sources[0x55]	6539	1			T1	5		T3	12		T7	1
valid_sources[0x56]	5530	1			T1	23		T2	1		T3	14
valid_sources[0x57]	3695	1			T1	1		T3	5		T11	81
valid_sources[0x58]	3052	1			T3	10		T4	1		T7	4
valid_sources[0x59]	3524	1			T1	5		T3	8		T4	1
valid_sources[0x5a]	3566	1			T1	25		T3	13		T4	4
valid_sources[0x5b]	4298	1			T1	5		T3	7		T4	5
valid_sources[0x5c]	3641	1			T1	11		T3	5		T9	70
valid_sources[0x5d]	3908	1			T1	3		T3	11		T4	1
valid_sources[0x5e]	3172	1			T3	4		T4	17		T7	2
valid_sources[0x5f]	4290	1			T1	7		T3	11		T4	5
valid_sources[0x60]	3788	1			T1	36		T3	6		T4	2
valid_sources[0x61]	3490	1			T1	23		T3	10		T7	4
valid_sources[0x62]	3859	1			T1	46		T3	7		T10	1
valid_sources[0x63]	8353	1			T3	15		T4	9		T7	1
valid_sources[0x64]	4183	1			T1	3		T3	6		T7	1
valid_sources[0x65]	3366	1			T1	7		T3	10		T4	1
valid_sources[0x66]	3174	1			T1	9		T3	16		T4	6
valid_sources[0x67]	6796	1			T1	23		T3	12		T11	114
valid_sources[0x68]	3841	1			T1	20		T3	14		T4	10
valid_sources[0x69]	6278	1			T3	10		T4	3		T7	4
valid_sources[0x6a]	3801	1			T1	4		T3	7		T4	4
valid_sources[0x6b]	3209	1			T1	1		T2	19		T3	10
valid_sources[0x6c]	3778	1			T1	4		T3	6		T4	5
valid_sources[0x6d]	3345	1			T1	54		T3	10		T4	1
valid_sources[0x6e]	3482	1			T1	10		T3	14		T4	6
valid_sources[0x6f]	3826	1			T1	10		T3	12		T7	1
valid_sources[0x70]	4321	1			T1	13		T3	8		T4	18
valid_sources[0x71]	3695	1			T3	13		T7	1		T10	3
valid_sources[0x72]	4924	1			T3	20		T4	2		T6	2
valid_sources[0x73]	4322	1			T1	26		T3	11		T7	1
valid_sources[0x74]	3779	1			T3	14		T7	1		T9	154
valid_sources[0x75]	4195	1			T1	13		T3	17		T4	13
valid_sources[0x76]	2979	1			T1	14		T3	16		T4	6
valid_sources[0x77]	3741	1			T1	14		T3	7		T4	9
valid_sources[0x78]	3568	1			T1	24		T3	10		T4	17
valid_sources[0x79]	3713	1			T1	23		T3	9		T4	2
valid_sources[0x7a]	2990	1			T3	8		T7	1		T11	105
valid_sources[0x7b]	4365	1			T3	13		T7	1		T10	6
valid_sources[0x7c]	3284	1			T1	27		T3	11		T7	1
valid_sources[0x7d]	5324	1			T1	4		T3	10		T4	16
valid_sources[0x7e]	3035	1			T1	20		T2	24		T3	8
valid_sources[0x7f]	3214	1			T1	11		T3	15		T7	4
valid_sources[0x80]	3767	1			T1	14		T3	8		T4	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

254772

1

T1

875

T2

42

T3

659

values[0x0]

all_enables

biggest_size

83170

1

T1

214

T2

20

T3

213

values[0x1]

all_enables

biggest_size

44468

1

T1

99

T2

12

T3

96