Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T9

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55711368	8817	0	0
CascadeEffAonToRstPorAboveRise_A	55711368	8817	0	0
CascadeEffAonToRstPorIoAboveFall_A	53481036	8817	0	0
CascadeEffAonToRstPorIoAboveRise_A	53481036	8817	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26741421	8817	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26741421	8817	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13370420	8817	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13370420	8817	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26741292	8817	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26741292	8817	0	0
CascadeLcToLcAboveFall_A	55711368	22437	0	0
CascadeLcToLcAboveRise_A	55711368	22437	0	0
CascadeLcToLcAonAboveFall_A	1689213	22437	0	0
CascadeLcToLcAonAboveRise_A	1689213	22437	0	0
CascadeLcToLcShadowedAboveFall_A	55711368	22437	0	0
CascadeLcToLcShadowedAboveRise_A	55711368	22437	0	0
CascadePorToAonAboveFall_A	1689213	6867	0	0
CascadeSysToSysAboveFall_A	55711368	22437	0	0
CascadeSysToSysAboveRise_A	55711368	22437	0	0
ScanRstToAonRise_A	1689213	239	0	0
StablePorToAonRise_A	1689213	8817	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11863167	22437	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11863167	22437	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11863167	22437	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11863167	22437	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13370420	22437	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13370420	22437	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11863167	22437	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11863167	22437	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11863167	22437	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11863167	22437	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	8817	0	0
T1	211762	28	0	0
T2	18068	2	0	0
T3	138936	16	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	2	0	0
T8	24378	8	0	0
T9	788481	104	0	0
T10	10560	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	8817	0	0
T1	211762	28	0	0
T2	18068	2	0	0
T3	138936	16	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	2	0	0
T8	24378	8	0	0
T9	788481	104	0	0
T10	10560	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53481036	8817	0	0
T1	203298	28	0	0
T2	17351	2	0	0
T3	133375	16	0	0
T4	36570	1	0	0
T5	6590	1	0	0
T6	6901	1	0	0
T7	10684	2	0	0
T8	23434	8	0	0
T9	756934	104	0	0
T10	10136	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53481036	8817	0	0
T1	203298	28	0	0
T2	17351	2	0	0
T3	133375	16	0	0
T4	36570	1	0	0
T5	6590	1	0	0
T6	6901	1	0	0
T7	10684	2	0	0
T8	23434	8	0	0
T9	756934	104	0	0
T10	10136	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741421	8817	0	0
T1	101641	28	0	0
T2	8673	2	0	0
T3	66691	16	0	0
T4	18285	1	0	0
T5	3294	1	0	0
T6	3450	1	0	0
T7	5339	2	0	0
T8	11711	8	0	0
T9	378476	104	0	0
T10	5070	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741421	8817	0	0
T1	101641	28	0	0
T2	8673	2	0	0
T3	66691	16	0	0
T4	18285	1	0	0
T5	3294	1	0	0
T6	3450	1	0	0
T7	5339	2	0	0
T8	11711	8	0	0
T9	378476	104	0	0
T10	5070	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	8817	0	0
T1	50827	28	0	0
T2	4336	2	0	0
T3	33344	16	0	0
T4	9142	1	0	0
T5	1647	1	0	0
T6	1725	1	0	0
T7	2669	2	0	0
T8	5854	8	0	0
T9	189233	104	0	0
T10	2533	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	8817	0	0
T1	50827	28	0	0
T2	4336	2	0	0
T3	33344	16	0	0
T4	9142	1	0	0
T5	1647	1	0	0
T6	1725	1	0	0
T7	2669	2	0	0
T8	5854	8	0	0
T9	189233	104	0	0
T10	2533	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741292	8817	0	0
T1	101652	28	0	0
T2	8674	2	0	0
T3	66691	16	0	0
T4	18285	1	0	0
T5	3294	1	0	0
T6	3450	1	0	0
T7	5339	2	0	0
T8	11707	8	0	0
T9	378517	104	0	0
T10	5071	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741292	8817	0	0
T1	101652	28	0	0
T2	8674	2	0	0
T3	66691	16	0	0
T4	18285	1	0	0
T5	3294	1	0	0
T6	3450	1	0	0
T7	5339	2	0	0
T8	11707	8	0	0
T9	378517	104	0	0
T10	5071	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	22437	0	0
T1	211762	58	0	0
T2	18068	6	0	0
T3	138936	55	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	6	0	0
T8	24378	8	0	0
T9	788481	285	0	0
T10	10560	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	22437	0	0
T1	211762	58	0	0
T2	18068	6	0	0
T3	138936	55	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	6	0	0
T8	24378	8	0	0
T9	788481	285	0	0
T10	10560	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	22437	0	0
T1	6421	58	0	0
T2	542	6	0	0
T3	4219	55	0	0
T4	1142	1	0	0
T5	204	1	0	0
T6	214	1	0	0
T7	332	6	0	0
T8	733	8	0	0
T9	23933	285	0	0
T10	315	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	22437	0	0
T1	6421	58	0	0
T2	542	6	0	0
T3	4219	55	0	0
T4	1142	1	0	0
T5	204	1	0	0
T6	214	1	0	0
T7	332	6	0	0
T8	733	8	0	0
T9	23933	285	0	0
T10	315	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	22437	0	0
T1	211762	58	0	0
T2	18068	6	0	0
T3	138936	55	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	6	0	0
T8	24378	8	0	0
T9	788481	285	0	0
T10	10560	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	22437	0	0
T1	211762	58	0	0
T2	18068	6	0	0
T3	138936	55	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	6	0	0
T8	24378	8	0	0
T9	788481	285	0	0
T10	10560	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	6867	0	0
T1	6421	13	0	0
T2	542	1	0	0
T3	4219	9	0	0
T4	1142	1	0	0
T5	204	1	0	0
T6	214	1	0	0
T7	332	1	0	0
T8	733	8	0	0
T9	23933	48	0	0
T10	315	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	22437	0	0
T1	211762	58	0	0
T2	18068	6	0	0
T3	138936	55	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	6	0	0
T8	24378	8	0	0
T9	788481	285	0	0
T10	10560	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55711368	22437	0	0
T1	211762	58	0	0
T2	18068	6	0	0
T3	138936	55	0	0
T4	38096	1	0	0
T5	6865	1	0	0
T6	7188	1	0	0
T7	11123	6	0	0
T8	24378	8	0	0
T9	788481	285	0	0
T10	10560	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	239	0	0
T1	6421	2	0	0
T2	542	0	0	0
T3	4219	0	0	0
T4	1142	0	0	0
T5	204	0	0	0
T6	214	0	0	0
T7	332	0	0	0
T8	733	0	0	0
T9	23933	9	0	0
T10	315	0	0	0
T11	0	14	0	0
T25	0	3	0	0
T44	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T52	0	4	0	0
T93	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	8817	0	0
T1	6421	28	0	0
T2	542	2	0	0
T3	4219	16	0	0
T4	1142	1	0	0
T5	204	1	0	0
T6	214	1	0	0
T7	332	2	0	0
T8	733	8	0	0
T9	23933	104	0	0
T10	315	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	22437	0	0
T1	50827	58	0	0
T2	4336	6	0	0
T3	33344	55	0	0
T4	9142	1	0	0
T5	1647	1	0	0
T6	1725	1	0	0
T7	2669	6	0	0
T8	5854	8	0	0
T9	189233	285	0	0
T10	2533	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	22437	0	0
T1	50827	58	0	0
T2	4336	6	0	0
T3	33344	55	0	0
T4	9142	1	0	0
T5	1647	1	0	0
T6	1725	1	0	0
T7	2669	6	0	0
T8	5854	8	0	0
T9	189233	285	0	0
T10	2533	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11863167	22437	0	0
T1	45207	58	0	0
T2	4142	6	0	0
T3	28119	55	0	0
T4	9075	1	0	0
T5	1580	1	0	0
T6	1658	1	0	0
T7	2527	6	0	0
T8	5692	8	0	0
T9	163798	285	0	0
T10	2439	6	0	0