Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13370420	14509	0	0
gen_assertions[0].RstEnOn_A	13370420	1069	0	0
gen_assertions[0].RstNOff_A	13370420	14509	0	0
gen_assertions[0].RstNOn_A	13370420	1069	0	0
gen_assertions[1].RstEnOff_A	53481036	13227	0	0
gen_assertions[1].RstEnOn_A	53481036	1065	0	0
gen_assertions[1].RstNOff_A	53481036	13227	0	0
gen_assertions[1].RstNOn_A	53481036	1065	0	0
gen_assertions[2].RstEnOff_A	26741421	13267	0	0
gen_assertions[2].RstEnOn_A	26741421	1055	0	0
gen_assertions[2].RstNOff_A	26741421	13267	0	0
gen_assertions[2].RstNOn_A	26741421	1055	0	0
gen_assertions[3].RstEnOff_A	26741292	13311	0	0
gen_assertions[3].RstEnOn_A	26741292	1079	0	0
gen_assertions[3].RstNOff_A	26741292	13311	0	0
gen_assertions[3].RstNOn_A	26741292	1079	0	0
gen_assertions[4].RstEnOff_A	1689213	22243	0	0
gen_assertions[4].RstEnOn_A	1689213	1156	0	0
gen_assertions[4].RstNOff_A	1689213	22243	0	0
gen_assertions[4].RstNOn_A	1689213	1156	0	0
gen_assertions[5].RstEnOff_A	13370420	14756	0	0
gen_assertions[5].RstEnOn_A	13370420	1180	0	0
gen_assertions[5].RstNOff_A	13370420	14756	0	0
gen_assertions[5].RstNOn_A	13370420	1180	0	0
gen_assertions[6].RstEnOff_A	13370420	14811	0	0
gen_assertions[6].RstEnOn_A	13370420	1233	0	0
gen_assertions[6].RstNOff_A	13370420	14811	0	0
gen_assertions[6].RstNOn_A	13370420	1233	0	0
gen_assertions[7].RstEnOff_A	13370420	14878	0	0
gen_assertions[7].RstEnOn_A	13370420	1310	0	0
gen_assertions[7].RstNOff_A	13370420	14878	0	0
gen_assertions[7].RstNOn_A	13370420	1310	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14509	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	1	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	4	0	0
T8	5854	0	0	0
T9	189233	189	0	0
T10	2533	4	0	0
T11	0	309	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1069	0	0
T4	9142	1	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	0	0	0
T8	5854	0	0	0
T9	189233	8	0	0
T10	2533	0	0	0
T11	172906	38	0	0
T12	2397	0	0	0
T13	6409	1	0	0
T25	0	10	0	0
T26	0	2	0	0
T27	0	8	0	0
T52	0	6	0	0
T53	0	6	0	0
T72	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14509	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	1	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	4	0	0
T8	5854	0	0	0
T9	189233	189	0	0
T10	2533	4	0	0
T11	0	309	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1069	0	0
T4	9142	1	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	0	0	0
T8	5854	0	0	0
T9	189233	8	0	0
T10	2533	0	0	0
T11	172906	38	0	0
T12	2397	0	0	0
T13	6409	1	0	0
T25	0	10	0	0
T26	0	2	0	0
T27	0	8	0	0
T52	0	6	0	0
T53	0	6	0	0
T72	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53481036	13227	0	0
T1	203298	30	0	0
T2	17351	4	0	0
T3	133375	36	0	0
T4	36570	3	0	0
T5	6590	0	0	0
T6	6901	0	0	0
T7	10684	5	0	0
T8	23434	0	0	0
T9	756934	172	0	0
T10	10136	3	0	0
T11	0	277	0	0
T13	0	16	0	0
T14	0	23	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53481036	1065	0	0
T4	36570	3	0	0
T5	6590	0	0	0
T6	6901	0	0	0
T7	10684	1	0	0
T8	23434	0	0	0
T9	756934	8	0	0
T10	10136	0	0	0
T11	691594	36	0	0
T12	9592	0	0	0
T13	25640	0	0	0
T25	0	13	0	0
T27	0	8	0	0
T52	0	8	0	0
T53	0	6	0	0
T72	0	4	0	0
T76	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53481036	13227	0	0
T1	203298	30	0	0
T2	17351	4	0	0
T3	133375	36	0	0
T4	36570	3	0	0
T5	6590	0	0	0
T6	6901	0	0	0
T7	10684	5	0	0
T8	23434	0	0	0
T9	756934	172	0	0
T10	10136	3	0	0
T11	0	277	0	0
T13	0	16	0	0
T14	0	23	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53481036	1065	0	0
T4	36570	3	0	0
T5	6590	0	0	0
T6	6901	0	0	0
T7	10684	1	0	0
T8	23434	0	0	0
T9	756934	8	0	0
T10	10136	0	0	0
T11	691594	36	0	0
T12	9592	0	0	0
T13	25640	0	0	0
T25	0	13	0	0
T27	0	8	0	0
T52	0	8	0	0
T53	0	6	0	0
T72	0	4	0	0
T76	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741421	13267	0	0
T1	101641	30	0	0
T2	8673	4	0	0
T3	66691	36	0	0
T4	18285	3	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	4	0	0
T8	11711	0	0	0
T9	378476	174	0	0
T10	5070	3	0	0
T11	0	282	0	0
T13	0	16	0	0
T14	0	23	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741421	1055	0	0
T4	18285	3	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	0	0	0
T8	11711	0	0	0
T9	378476	10	0	0
T10	5070	0	0	0
T11	345847	40	0	0
T12	4799	0	0	0
T13	12819	0	0	0
T25	0	11	0	0
T27	0	10	0	0
T30	0	1	0	0
T46	0	12	0	0
T52	0	8	0	0
T53	0	7	0	0
T72	0	5	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741421	13267	0	0
T1	101641	30	0	0
T2	8673	4	0	0
T3	66691	36	0	0
T4	18285	3	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	4	0	0
T8	11711	0	0	0
T9	378476	174	0	0
T10	5070	3	0	0
T11	0	282	0	0
T13	0	16	0	0
T14	0	23	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741421	1055	0	0
T4	18285	3	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	0	0	0
T8	11711	0	0	0
T9	378476	10	0	0
T10	5070	0	0	0
T11	345847	40	0	0
T12	4799	0	0	0
T13	12819	0	0	0
T25	0	11	0	0
T27	0	10	0	0
T30	0	1	0	0
T46	0	12	0	0
T52	0	8	0	0
T53	0	7	0	0
T72	0	5	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741292	13311	0	0
T1	101652	30	0	0
T2	8674	4	0	0
T3	66691	36	0	0
T4	18285	5	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	5	0	0
T8	11707	0	0	0
T9	378517	175	0	0
T10	5071	3	0	0
T11	0	276	0	0
T13	0	16	0	0
T14	0	23	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741292	1079	0	0
T4	18285	5	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	1	0	0
T8	11707	0	0	0
T9	378517	11	0	0
T10	5071	0	0	0
T11	345809	34	0	0
T12	4799	0	0	0
T13	12819	0	0	0
T25	0	13	0	0
T27	0	10	0	0
T46	0	15	0	0
T52	0	7	0	0
T53	0	8	0	0
T72	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741292	13311	0	0
T1	101652	30	0	0
T2	8674	4	0	0
T3	66691	36	0	0
T4	18285	5	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	5	0	0
T8	11707	0	0	0
T9	378517	175	0	0
T10	5071	3	0	0
T11	0	276	0	0
T13	0	16	0	0
T14	0	23	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26741292	1079	0	0
T4	18285	5	0	0
T5	3294	0	0	0
T6	3450	0	0	0
T7	5339	1	0	0
T8	11707	0	0	0
T9	378517	11	0	0
T10	5071	0	0	0
T11	345809	34	0	0
T12	4799	0	0	0
T13	12819	0	0	0
T25	0	13	0	0
T27	0	10	0	0
T46	0	15	0	0
T52	0	7	0	0
T53	0	8	0	0
T72	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	22243	0	0
T1	6421	58	0	0
T2	542	6	0	0
T3	4219	55	0	0
T4	1142	7	0	0
T5	204	1	0	0
T6	214	1	0	0
T7	332	6	0	0
T8	733	2	0	0
T9	23933	292	0	0
T10	315	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	1156	0	0
T4	1142	6	0	0
T5	204	0	0	0
T6	214	0	0	0
T7	332	0	0	0
T8	733	0	0	0
T9	23933	10	0	0
T10	315	0	0	0
T11	22262	36	0	0
T12	299	0	0	0
T13	799	0	0	0
T25	0	11	0	0
T27	0	10	0	0
T30	0	1	0	0
T46	0	11	0	0
T52	0	6	0	0
T53	0	6	0	0
T72	0	8	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	22243	0	0
T1	6421	58	0	0
T2	542	6	0	0
T3	4219	55	0	0
T4	1142	7	0	0
T5	204	1	0	0
T6	214	1	0	0
T7	332	6	0	0
T8	733	2	0	0
T9	23933	292	0	0
T10	315	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1689213	1156	0	0
T4	1142	6	0	0
T5	204	0	0	0
T6	214	0	0	0
T7	332	0	0	0
T8	733	0	0	0
T9	23933	10	0	0
T10	315	0	0	0
T11	22262	36	0	0
T12	299	0	0	0
T13	799	0	0	0
T25	0	11	0	0
T27	0	10	0	0
T30	0	1	0	0
T46	0	11	0	0
T52	0	6	0	0
T53	0	6	0	0
T72	0	8	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14756	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	4	0	0
T8	5854	0	0	0
T9	189233	190	0	0
T10	2533	4	0	0
T11	0	313	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1180	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	0	0	0
T8	5854	0	0	0
T9	189233	10	0	0
T10	2533	0	0	0
T11	172906	41	0	0
T12	2397	0	0	0
T13	6409	0	0	0
T25	0	11	0	0
T27	0	13	0	0
T29	0	1	0	0
T46	0	16	0	0
T52	0	8	0	0
T53	0	9	0	0
T72	0	9	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14756	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	4	0	0
T8	5854	0	0	0
T9	189233	190	0	0
T10	2533	4	0	0
T11	0	313	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1180	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	0	0	0
T8	5854	0	0	0
T9	189233	10	0	0
T10	2533	0	0	0
T11	172906	41	0	0
T12	2397	0	0	0
T13	6409	0	0	0
T25	0	11	0	0
T27	0	13	0	0
T29	0	1	0	0
T46	0	16	0	0
T52	0	8	0	0
T53	0	9	0	0
T72	0	9	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14811	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	5	0	0
T8	5854	0	0	0
T9	189233	191	0	0
T10	2533	4	0	0
T11	0	304	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1233	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	1	0	0
T8	5854	0	0	0
T9	189233	11	0	0
T10	2533	0	0	0
T11	172906	34	0	0
T12	2397	0	0	0
T13	6409	0	0	0
T25	0	15	0	0
T27	0	12	0	0
T29	0	1	0	0
T52	0	7	0	0
T53	0	9	0	0
T72	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14811	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	5	0	0
T8	5854	0	0	0
T9	189233	191	0	0
T10	2533	4	0	0
T11	0	304	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1233	0	0
T4	9142	7	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	1	0	0
T8	5854	0	0	0
T9	189233	11	0	0
T10	2533	0	0	0
T11	172906	34	0	0
T12	2397	0	0	0
T13	6409	0	0	0
T25	0	15	0	0
T27	0	12	0	0
T29	0	1	0	0
T52	0	7	0	0
T53	0	9	0	0
T72	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14878	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	9	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	4	0	0
T8	5854	0	0	0
T9	189233	191	0	0
T10	2533	5	0	0
T11	0	310	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1310	0	0
T4	9142	9	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	0	0	0
T8	5854	0	0	0
T9	189233	11	0	0
T10	2533	1	0	0
T11	172906	40	0	0
T12	2397	0	0	0
T13	6409	0	0	0
T25	0	18	0	0
T27	0	11	0	0
T52	0	6	0	0
T53	0	12	0	0
T72	0	11	0	0
T76	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	14878	0	0
T1	50827	30	0	0
T2	4336	4	0	0
T3	33344	39	0	0
T4	9142	9	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	4	0	0
T8	5854	0	0	0
T9	189233	191	0	0
T10	2533	5	0	0
T11	0	310	0	0
T12	0	4	0	0
T13	0	20	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13370420	1310	0	0
T4	9142	9	0	0
T5	1647	0	0	0
T6	1725	0	0	0
T7	2669	0	0	0
T8	5854	0	0	0
T9	189233	11	0	0
T10	2533	1	0	0
T11	172906	40	0	0
T12	2397	0	0	0
T13	6409	0	0	0
T25	0	18	0	0
T27	0	11	0	0
T52	0	6	0	0
T53	0	12	0	0
T72	0	11	0	0
T76	0	1	0	0