Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12672012	8984	0	0
alert_regwen_rd_A	12672012	4108	0	0
cpu_regwen_rd_A	12672012	4303	0	0
sw_rst_ctrl_n_0_rd_A	12672012	8881	0	0
sw_rst_ctrl_n_1_rd_A	12672012	8533	0	0
sw_rst_ctrl_n_2_rd_A	12672012	8376	0	0
sw_rst_ctrl_n_3_rd_A	12672012	8445	0	0
sw_rst_ctrl_n_4_rd_A	12672012	8445	0	0
sw_rst_ctrl_n_5_rd_A	12672012	8512	0	0
sw_rst_ctrl_n_6_rd_A	12672012	8635	0	0
sw_rst_ctrl_n_7_rd_A	12672012	8780	0	0
sw_rst_regwen_0_rd_A	12672012	4808	0	0
sw_rst_regwen_1_rd_A	12672012	4890	0	0
sw_rst_regwen_2_rd_A	12672012	4667	0	0
sw_rst_regwen_3_rd_A	12672012	4829	0	0
sw_rst_regwen_4_rd_A	12672012	4794	0	0
sw_rst_regwen_5_rd_A	12672012	4933	0	0
sw_rst_regwen_6_rd_A	12672012	4815	0	0
sw_rst_regwen_7_rd_A	12672012	4985	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8984	0	0
T75	9995	3	0	0
T77	2555	4	0	0
T78	9386	366	0	0
T79	10216	227	0	0
T80	21676	8	0	0
T94	9084	304	0	0
T95	11324	631	0	0
T96	21106	4	0	0
T97	3821	11	0	0
T100	10665	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4108	0	0
T1	45207	86	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	0	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	88	0	0
T104	0	289	0	0
T105	0	397	0	0
T106	0	92	0	0
T124	0	39	0	0
T125	0	163	0	0
T126	0	57	0	0
T127	0	90	0	0
T128	0	376	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4303	0	0
T1	45207	110	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	0	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	99	0	0
T104	0	313	0	0
T105	0	377	0	0
T106	0	137	0	0
T124	0	46	0	0
T125	0	178	0	0
T126	0	58	0	0
T127	0	79	0	0
T128	0	412	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8881	0	0
T1	45207	81	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	118	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	37	0	0
T44	0	98	0	0
T68	0	8	0	0
T104	0	545	0	0
T105	0	677	0	0
T106	0	279	0	0
T124	0	51	0	0
T129	0	114	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8533	0	0
T1	45207	85	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	123	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	18	0	0
T44	0	91	0	0
T68	0	12	0	0
T104	0	493	0	0
T105	0	694	0	0
T106	0	230	0	0
T124	0	44	0	0
T129	0	99	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8376	0	0
T1	45207	92	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	155	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	25	0	0
T44	0	102	0	0
T68	0	17	0	0
T104	0	585	0	0
T105	0	654	0	0
T106	0	190	0	0
T124	0	31	0	0
T129	0	122	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8445	0	0
T1	45207	97	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	106	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	56	0	0
T44	0	86	0	0
T68	0	10	0	0
T104	0	511	0	0
T105	0	655	0	0
T106	0	214	0	0
T124	0	53	0	0
T129	0	104	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8445	0	0
T1	45207	98	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	101	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	42	0	0
T44	0	85	0	0
T68	0	20	0	0
T104	0	449	0	0
T105	0	655	0	0
T106	0	222	0	0
T124	0	67	0	0
T129	0	113	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8512	0	0
T1	45207	127	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	124	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	33	0	0
T44	0	81	0	0
T68	0	6	0	0
T104	0	482	0	0
T105	0	610	0	0
T106	0	252	0	0
T124	0	48	0	0
T129	0	101	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8635	0	0
T1	45207	84	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	146	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	31	0	0
T44	0	115	0	0
T68	0	5	0	0
T104	0	422	0	0
T105	0	697	0	0
T106	0	222	0	0
T124	0	44	0	0
T129	0	116	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	8780	0	0
T1	45207	95	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	123	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T13	0	55	0	0
T44	0	106	0	0
T68	0	12	0	0
T104	0	542	0	0
T105	0	640	0	0
T106	0	254	0	0
T124	0	53	0	0
T129	0	124	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4808	0	0
T1	45207	115	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	27	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	105	0	0
T68	0	7	0	0
T104	0	284	0	0
T105	0	373	0	0
T106	0	111	0	0
T124	0	29	0	0
T129	0	37	0	0
T130	0	43	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4890	0	0
T1	45207	93	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	21	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	78	0	0
T68	0	9	0	0
T104	0	339	0	0
T105	0	380	0	0
T106	0	118	0	0
T124	0	57	0	0
T129	0	28	0	0
T130	0	37	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4667	0	0
T1	45207	66	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	28	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	87	0	0
T68	0	6	0	0
T104	0	286	0	0
T105	0	303	0	0
T106	0	82	0	0
T124	0	40	0	0
T129	0	31	0	0
T130	0	18	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4829	0	0
T1	45207	121	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	38	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	102	0	0
T68	0	4	0	0
T104	0	307	0	0
T105	0	335	0	0
T106	0	121	0	0
T124	0	70	0	0
T129	0	26	0	0
T130	0	36	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4794	0	0
T1	45207	138	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	41	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	85	0	0
T104	0	296	0	0
T105	0	369	0	0
T106	0	134	0	0
T124	0	41	0	0
T129	0	35	0	0
T130	0	37	0	0
T131	0	9	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4933	0	0
T1	45207	136	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	28	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	80	0	0
T68	0	11	0	0
T104	0	320	0	0
T105	0	380	0	0
T106	0	165	0	0
T124	0	38	0	0
T129	0	33	0	0
T130	0	35	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4815	0	0
T1	45207	106	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	24	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	82	0	0
T104	0	301	0	0
T105	0	398	0	0
T106	0	126	0	0
T124	0	47	0	0
T129	0	47	0	0
T130	0	36	0	0
T131	0	29	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12672012	4985	0	0
T1	45207	82	0	0
T2	4142	0	0	0
T3	28119	0	0	0
T4	9075	32	0	0
T5	1580	0	0	0
T6	1658	0	0	0
T7	2527	0	0	0
T8	5692	0	0	0
T9	163798	0	0	0
T10	2439	0	0	0
T44	0	78	0	0
T68	0	6	0	0
T104	0	317	0	0
T105	0	388	0	0
T106	0	136	0	0
T124	0	47	0	0
T129	0	32	0	0
T130	0	41	0	0