Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	571207	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

344625

1

T1

115

T3

146

T5

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	489175	1			T1	136		T3	186		T6	1500
values[0x0]	213034	1			T1	75		T3	101		T5	20
values[0x1]	213623	1			T1	69		T3	92		T5	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	479742	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

436090

1

T1

133

T3

184

T5

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4660	1			T3	1		T6	28		T10	440
valid_sources[0x01]	3631	1			T1	1		T3	3		T6	16
valid_sources[0x02]	7100	1			T1	1		T3	1		T6	20
valid_sources[0x03]	3350	1			T1	3		T3	4		T6	12
valid_sources[0x04]	4511	1			T3	3		T6	6		T30	3
valid_sources[0x05]	3654	1			T3	2		T6	21		T10	197
valid_sources[0x06]	3440	1			T1	3		T3	3		T6	22
valid_sources[0x07]	3800	1			T1	1		T3	2		T6	19
valid_sources[0x08]	3261	1			T3	2		T6	4		T10	104
valid_sources[0x09]	3298	1			T3	2		T6	2		T10	105
valid_sources[0x0a]	3201	1			T1	1		T3	5		T6	7
valid_sources[0x0b]	4746	1			T6	7		T27	21		T83	2
valid_sources[0x0c]	2901	1			T3	2		T6	22		T9	57
valid_sources[0x0d]	3585	1			T3	1		T6	14		T7	1
valid_sources[0x0e]	3388	1			T3	2		T6	10		T10	449
valid_sources[0x0f]	4084	1			T1	3		T3	1		T6	22
valid_sources[0x10]	3565	1			T1	2		T3	1		T6	5
valid_sources[0x11]	3613	1			T1	1		T6	22		T10	9
valid_sources[0x12]	2888	1			T3	1		T6	31		T7	2
valid_sources[0x13]	3782	1			T1	1		T3	4		T6	9
valid_sources[0x14]	3402	1			T1	2		T6	6		T7	1
valid_sources[0x15]	3598	1			T1	3		T3	1		T6	10
valid_sources[0x16]	4502	1			T1	3		T3	2		T6	2
valid_sources[0x17]	4247	1			T3	4		T6	7		T10	241
valid_sources[0x18]	2692	1			T3	3		T6	9		T30	2
valid_sources[0x19]	2907	1			T1	1		T5	2		T6	15
valid_sources[0x1a]	3104	1			T1	1		T6	19		T26	61
valid_sources[0x1b]	3308	1			T1	2		T3	1		T6	8
valid_sources[0x1c]	3660	1			T1	1		T6	17		T7	3
valid_sources[0x1d]	3384	1			T1	4		T6	12		T10	2
valid_sources[0x1e]	3079	1			T1	1		T3	1		T5	2
valid_sources[0x1f]	3058	1			T1	4		T6	14		T10	118
valid_sources[0x20]	3123	1			T1	2		T3	3		T6	10
valid_sources[0x21]	3002	1			T1	2		T6	12		T7	1
valid_sources[0x22]	3542	1			T1	4		T6	20		T26	113
valid_sources[0x23]	3401	1			T1	2		T3	5		T6	3
valid_sources[0x24]	2919	1			T3	2		T6	12		T27	7
valid_sources[0x25]	2957	1			T1	2		T3	3		T6	18
valid_sources[0x26]	3658	1			T1	1		T3	2		T6	27
valid_sources[0x27]	3027	1			T6	5		T26	367		T27	4
valid_sources[0x28]	3065	1			T1	1		T3	1		T6	28
valid_sources[0x29]	3228	1			T1	1		T3	1		T6	20
valid_sources[0x2a]	3995	1			T6	6		T7	1		T10	129
valid_sources[0x2b]	3732	1			T6	16		T7	1		T10	112
valid_sources[0x2c]	2892	1			T3	3		T6	13		T7	1
valid_sources[0x2d]	3014	1			T5	1		T6	9		T7	1
valid_sources[0x2e]	3865	1			T1	2		T6	12		T10	8
valid_sources[0x2f]	3166	1			T1	1		T3	2		T6	8
valid_sources[0x30]	3220	1			T1	2		T3	2		T6	8
valid_sources[0x31]	3798	1			T1	3		T3	2		T6	5
valid_sources[0x32]	3062	1			T3	1		T6	7		T26	70
valid_sources[0x33]	2683	1			T1	1		T3	1		T6	11
valid_sources[0x34]	4279	1			T3	3		T6	7		T7	2
valid_sources[0x35]	3797	1			T1	1		T3	2		T6	5
valid_sources[0x36]	3265	1			T1	4		T3	2		T6	8
valid_sources[0x37]	3074	1			T1	1		T6	8		T27	9
valid_sources[0x38]	3705	1			T6	9		T26	9		T27	4
valid_sources[0x39]	3532	1			T1	1		T6	8		T10	13
valid_sources[0x3a]	3508	1			T3	1		T6	9		T10	440
valid_sources[0x3b]	2743	1			T1	1		T3	3		T6	21
valid_sources[0x3c]	3443	1			T1	1		T3	1		T6	8
valid_sources[0x3d]	3166	1			T1	1		T6	10		T10	196
valid_sources[0x3e]	3172	1			T1	1		T3	1		T5	2
valid_sources[0x3f]	3190	1			T1	2		T3	1		T6	20
valid_sources[0x40]	2992	1			T3	4		T6	9		T10	64
valid_sources[0x41]	2244	1			T1	2		T6	21		T7	1
valid_sources[0x42]	3272	1			T6	18		T7	1		T10	15
valid_sources[0x43]	3341	1			T6	3		T10	57		T27	8
valid_sources[0x44]	3667	1			T3	1		T6	13		T7	1
valid_sources[0x45]	2733	1			T3	2		T6	14		T10	1
valid_sources[0x46]	2613	1			T3	2		T6	9		T7	2
valid_sources[0x47]	4802	1			T1	2		T3	1		T6	23
valid_sources[0x48]	3374	1			T3	2		T6	21		T10	113
valid_sources[0x49]	2901	1			T1	1		T6	21		T7	1
valid_sources[0x4a]	3627	1			T1	1		T3	1		T6	30
valid_sources[0x4b]	3089	1			T5	2		T6	12		T27	19
valid_sources[0x4c]	3039	1			T1	2		T6	15		T10	8
valid_sources[0x4d]	4396	1			T1	1		T3	4		T6	33
valid_sources[0x4e]	2832	1			T1	3		T5	2		T6	20
valid_sources[0x4f]	3705	1			T3	2		T6	14		T7	1
valid_sources[0x50]	2628	1			T1	1		T3	1		T6	3
valid_sources[0x51]	3049	1			T1	1		T6	13		T27	1
valid_sources[0x52]	3067	1			T1	2		T3	1		T6	22
valid_sources[0x53]	3718	1			T3	3		T6	13		T7	1
valid_sources[0x54]	3459	1			T1	1		T3	1		T6	9
valid_sources[0x55]	4459	1			T1	2		T3	1		T6	9
valid_sources[0x56]	2873	1			T1	1		T3	3		T6	13
valid_sources[0x57]	3848	1			T1	3		T6	13		T7	1
valid_sources[0x58]	3786	1			T3	1		T6	10		T7	1
valid_sources[0x59]	3833	1			T1	2		T6	8		T10	9
valid_sources[0x5a]	2829	1			T1	2		T6	12		T27	11
valid_sources[0x5b]	3196	1			T3	2		T6	2		T7	1
valid_sources[0x5c]	2757	1			T1	2		T6	3		T7	1
valid_sources[0x5d]	3438	1			T1	1		T3	3		T6	6
valid_sources[0x5e]	3382	1			T6	10		T26	70		T27	5
valid_sources[0x5f]	3128	1			T1	1		T6	3		T10	71
valid_sources[0x60]	4067	1			T1	2		T5	1		T6	4
valid_sources[0x61]	3434	1			T1	2		T3	4		T6	11
valid_sources[0x62]	3357	1			T1	2		T3	1		T6	12
valid_sources[0x63]	3107	1			T1	3		T6	11		T7	3
valid_sources[0x64]	4027	1			T3	4		T6	14		T7	1
valid_sources[0x65]	3178	1			T1	2		T6	9		T7	2
valid_sources[0x66]	3569	1			T1	3		T3	4		T6	18
valid_sources[0x67]	2999	1			T3	2		T6	6		T7	1
valid_sources[0x68]	3633	1			T3	1		T6	11		T7	1
valid_sources[0x69]	3410	1			T1	2		T3	1		T6	13
valid_sources[0x6a]	2885	1			T1	1		T3	1		T5	1
valid_sources[0x6b]	3822	1			T3	4		T6	17		T7	2
valid_sources[0x6c]	5278	1			T1	1		T6	12		T10	685
valid_sources[0x6d]	2949	1			T1	2		T6	12		T7	1
valid_sources[0x6e]	3468	1			T1	1		T3	2		T6	7
valid_sources[0x6f]	6291	1			T1	2		T3	2		T6	16
valid_sources[0x70]	3384	1			T1	1		T6	8		T10	156
valid_sources[0x71]	4638	1			T1	3		T3	2		T6	10
valid_sources[0x72]	5941	1			T1	3		T3	2		T6	9
valid_sources[0x73]	4493	1			T1	3		T3	3		T6	14
valid_sources[0x74]	2876	1			T3	1		T6	18		T10	13
valid_sources[0x75]	2823	1			T1	1		T3	2		T6	17
valid_sources[0x76]	3964	1			T3	4		T6	10		T10	281
valid_sources[0x77]	2998	1			T1	4		T3	1		T6	15
valid_sources[0x78]	4064	1			T1	2		T3	1		T6	21
valid_sources[0x79]	2500	1			T3	3		T6	3		T10	13
valid_sources[0x7a]	3722	1			T3	1		T6	16		T10	9
valid_sources[0x7b]	3018	1			T1	2		T3	5		T6	14
valid_sources[0x7c]	3137	1			T1	2		T6	8		T7	1
valid_sources[0x7d]	4187	1			T3	2		T6	12		T9	281
valid_sources[0x7e]	3655	1			T1	2		T6	7		T7	1
valid_sources[0x7f]	3343	1			T1	2		T3	4		T6	12
valid_sources[0x80]	3383	1			T1	1		T3	1		T6	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

229801

1

T1

78

T3

90

T6

671

values[0x0]

all_enables

biggest_size

74901

1

T1

22

T3

42

T5

8

values[0x1]

all_enables

biggest_size

39923

1

T1

15

T3

14

T5

1