Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11465488	12138	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11465488	112110	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11465488	6826388	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11465488	178952	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11465488	12138	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11465488	112110	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11465488	6826388	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11465488	178952	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	12138	0	0
T1	3801	15	0	0
T2	5669	0	0	0
T3	5606	4	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	75	0	0
T7	1868	6	0	0
T8	5309	0	0	0
T9	26014	41	0	0
T10	158172	340	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	112110	0	0
T1	3801	135	0	0
T2	5669	0	0	0
T3	5606	38	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	705	0	0
T7	1868	54	0	0
T8	5309	0	0	0
T9	26014	373	0	0
T10	158172	3076	0	0
T11	0	18	0	0
T13	0	37	0	0
T14	0	37	0	0
T25	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	6826388	0	0
T1	3801	2996	0	0
T2	5669	571	0	0
T3	5606	4625	0	0
T4	5452	565	0	0
T5	1921	1321	0	0
T6	26009	8793	0	0
T7	1868	1147	0	0
T8	5309	578	0	0
T9	26014	19605	0	0
T10	158172	77510	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	178952	0	0
T1	3801	231	0	0
T2	5669	0	0	0
T3	5606	78	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	1142	0	0
T7	1868	83	0	0
T8	5309	0	0	0
T9	26014	614	0	0
T10	158172	4865	0	0
T11	0	29	0	0
T13	0	67	0	0
T14	0	60	0	0
T25	0	68	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	12138	0	0
T1	3801	15	0	0
T2	5669	0	0	0
T3	5606	4	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	75	0	0
T7	1868	6	0	0
T8	5309	0	0	0
T9	26014	41	0	0
T10	158172	340	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	112110	0	0
T1	3801	135	0	0
T2	5669	0	0	0
T3	5606	38	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	705	0	0
T7	1868	54	0	0
T8	5309	0	0	0
T9	26014	373	0	0
T10	158172	3076	0	0
T11	0	18	0	0
T13	0	37	0	0
T14	0	37	0	0
T25	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	6826388	0	0
T1	3801	2996	0	0
T2	5669	571	0	0
T3	5606	4625	0	0
T4	5452	565	0	0
T5	1921	1321	0	0
T6	26009	8793	0	0
T7	1868	1147	0	0
T8	5309	578	0	0
T9	26014	19605	0	0
T10	158172	77510	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	178952	0	0
T1	3801	231	0	0
T2	5669	0	0	0
T3	5606	78	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	1142	0	0
T7	1868	83	0	0
T8	5309	0	0	0
T9	26014	614	0	0
T10	158172	4865	0	0
T11	0	29	0	0
T13	0	67	0	0
T14	0	60	0	0
T25	0	68	0	0