Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T9,T10,T25
1	0	Covered	T3,T9,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53677784	8548	0	0
CascadeEffAonToRstPorAboveRise_A	53677784	8548	0	0
CascadeEffAonToRstPorIoAboveFall_A	51528524	8548	0	0
CascadeEffAonToRstPorIoAboveRise_A	51528524	8548	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25765195	8548	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25765195	8548	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12882319	8548	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12882319	8548	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25765229	8548	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25765229	8548	0	0
CascadeLcToLcAboveFall_A	53677784	20686	0	0
CascadeLcToLcAboveRise_A	53677784	20686	0	0
CascadeLcToLcAonAboveFall_A	1625203	20686	0	0
CascadeLcToLcAonAboveRise_A	1625203	20686	0	0
CascadeLcToLcShadowedAboveFall_A	53677784	20686	0	0
CascadeLcToLcShadowedAboveRise_A	53677784	20686	0	0
CascadePorToAonAboveFall_A	1625203	6992	0	0
CascadeSysToSysAboveFall_A	53677784	20686	0	0
CascadeSysToSysAboveRise_A	53677784	20686	0	0
ScanRstToAonRise_A	1625203	184	0	0
StablePorToAonRise_A	1625203	8548	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11465488	20686	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11465488	20686	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11465488	20686	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11465488	20686	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12882319	20686	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12882319	20686	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11465488	20686	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11465488	20686	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11465488	20686	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11465488	20686	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	8548	0	0
T1	20516	1	0	0
T2	24300	8	0	0
T3	24139	2	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	27	0	0
T7	9513	1	0	0
T8	24379	8	0	0
T9	127760	12	0	0
T10	847823	177	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	8548	0	0
T1	20516	1	0	0
T2	24300	8	0	0
T3	24139	2	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	27	0	0
T7	9513	1	0	0
T8	24379	8	0	0
T9	127760	12	0	0
T10	847823	177	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	8548	0	0
T1	19696	1	0	0
T2	23322	8	0	0
T3	23175	2	0	0
T4	23229	8	0	0
T5	7952	1	0	0
T6	117056	27	0	0
T7	9131	1	0	0
T8	23426	8	0	0
T9	122626	12	0	0
T10	813887	177	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	8548	0	0
T1	19696	1	0	0
T2	23322	8	0	0
T3	23175	2	0	0
T4	23229	8	0	0
T5	7952	1	0	0
T6	117056	27	0	0
T7	9131	1	0	0
T8	23426	8	0	0
T9	122626	12	0	0
T10	813887	177	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	8548	0	0
T1	9847	1	0	0
T2	11660	8	0	0
T3	11588	2	0	0
T4	11616	8	0	0
T5	3976	1	0	0
T6	58545	27	0	0
T7	4565	1	0	0
T8	11704	8	0	0
T9	61317	12	0	0
T10	406944	177	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	8548	0	0
T1	9847	1	0	0
T2	11660	8	0	0
T3	11588	2	0	0
T4	11616	8	0	0
T5	3976	1	0	0
T6	58545	27	0	0
T7	4565	1	0	0
T8	11704	8	0	0
T9	61317	12	0	0
T10	406944	177	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	8548	0	0
T1	4923	1	0	0
T2	5829	8	0	0
T3	5794	2	0	0
T4	5806	8	0	0
T5	1987	1	0	0
T6	29272	27	0	0
T7	2282	1	0	0
T8	5854	8	0	0
T9	30659	12	0	0
T10	203486	177	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	8548	0	0
T1	4923	1	0	0
T2	5829	8	0	0
T3	5794	2	0	0
T4	5806	8	0	0
T5	1987	1	0	0
T6	29272	27	0	0
T7	2282	1	0	0
T8	5854	8	0	0
T9	30659	12	0	0
T10	203486	177	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	8548	0	0
T1	9847	1	0	0
T2	11661	8	0	0
T3	11588	2	0	0
T4	11611	8	0	0
T5	3977	1	0	0
T6	58549	27	0	0
T7	4565	1	0	0
T8	11709	8	0	0
T9	61314	12	0	0
T10	406956	177	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	8548	0	0
T1	9847	1	0	0
T2	11661	8	0	0
T3	11588	2	0	0
T4	11611	8	0	0
T5	3977	1	0	0
T6	58549	27	0	0
T7	4565	1	0	0
T8	11709	8	0	0
T9	61314	12	0	0
T10	406956	177	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	20686	0	0
T1	20516	16	0	0
T2	24300	8	0	0
T3	24139	6	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	102	0	0
T7	9513	7	0	0
T8	24379	8	0	0
T9	127760	53	0	0
T10	847823	517	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	20686	0	0
T1	20516	16	0	0
T2	24300	8	0	0
T3	24139	6	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	102	0	0
T7	9513	7	0	0
T8	24379	8	0	0
T9	127760	53	0	0
T10	847823	517	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	20686	0	0
T1	614	16	0	0
T2	730	8	0	0
T3	723	6	0	0
T4	728	8	0	0
T5	247	1	0	0
T6	3674	102	0	0
T7	285	7	0	0
T8	734	8	0	0
T9	3895	53	0	0
T10	26127	517	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	20686	0	0
T1	614	16	0	0
T2	730	8	0	0
T3	723	6	0	0
T4	728	8	0	0
T5	247	1	0	0
T6	3674	102	0	0
T7	285	7	0	0
T8	734	8	0	0
T9	3895	53	0	0
T10	26127	517	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	20686	0	0
T1	20516	16	0	0
T2	24300	8	0	0
T3	24139	6	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	102	0	0
T7	9513	7	0	0
T8	24379	8	0	0
T9	127760	53	0	0
T10	847823	517	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	20686	0	0
T1	20516	16	0	0
T2	24300	8	0	0
T3	24139	6	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	102	0	0
T7	9513	7	0	0
T8	24379	8	0	0
T9	127760	53	0	0
T10	847823	517	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	6992	0	0
T1	614	1	0	0
T2	730	8	0	0
T3	723	1	0	0
T4	728	8	0	0
T5	247	1	0	0
T6	3674	27	0	0
T7	285	1	0	0
T8	734	8	0	0
T9	3895	8	0	0
T10	26127	91	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	20686	0	0
T1	20516	16	0	0
T2	24300	8	0	0
T3	24139	6	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	102	0	0
T7	9513	7	0	0
T8	24379	8	0	0
T9	127760	53	0	0
T10	847823	517	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	20686	0	0
T1	20516	16	0	0
T2	24300	8	0	0
T3	24139	6	0	0
T4	24184	8	0	0
T5	8284	1	0	0
T6	121924	102	0	0
T7	9513	7	0	0
T8	24379	8	0	0
T9	127760	53	0	0
T10	847823	517	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	184	0	0
T9	3895	1	0	0
T10	26127	11	0	0
T11	267	0	0	0
T12	690	0	0	0
T13	447	0	0	0
T14	364	0	0	0
T24	743	0	0	0
T25	327	0	0	0
T26	27571	2	0	0
T27	3301	0	0	0
T86	0	3	0	0
T100	0	1	0	0
T103	0	1	0	0
T126	0	1	0	0
T143	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	8548	0	0
T1	614	1	0	0
T2	730	8	0	0
T3	723	2	0	0
T4	728	8	0	0
T5	247	1	0	0
T6	3674	27	0	0
T7	285	1	0	0
T8	734	8	0	0
T9	3895	12	0	0
T10	26127	177	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	20686	0	0
T1	4923	16	0	0
T2	5829	8	0	0
T3	5794	6	0	0
T4	5806	8	0	0
T5	1987	1	0	0
T6	29272	102	0	0
T7	2282	7	0	0
T8	5854	8	0	0
T9	30659	53	0	0
T10	203486	517	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	20686	0	0
T1	4923	16	0	0
T2	5829	8	0	0
T3	5794	6	0	0
T4	5806	8	0	0
T5	1987	1	0	0
T6	29272	102	0	0
T7	2282	7	0	0
T8	5854	8	0	0
T9	30659	53	0	0
T10	203486	517	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11465488	20686	0	0
T1	3801	16	0	0
T2	5669	8	0	0
T3	5606	6	0	0
T4	5452	8	0	0
T5	1921	1	0	0
T6	26009	102	0	0
T7	1868	7	0	0
T8	5309	8	0	0
T9	26014	53	0	0
T10	158172	517	0	0