Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T25,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T14,T25
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T25,T26
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T26,T59
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T26,T59
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12882319	12970	0	0
gen_assertions[0].RstEnOn_A	12882319	1029	0	0
gen_assertions[0].RstNOff_A	12882319	12970	0	0
gen_assertions[0].RstNOn_A	12882319	1029	0	0
gen_assertions[1].RstEnOff_A	51528524	11853	0	0
gen_assertions[1].RstEnOn_A	51528524	976	0	0
gen_assertions[1].RstNOff_A	51528524	11853	0	0
gen_assertions[1].RstNOn_A	51528524	976	0	0
gen_assertions[2].RstEnOff_A	25765195	11910	0	0
gen_assertions[2].RstEnOn_A	25765195	979	0	0
gen_assertions[2].RstNOff_A	25765195	11910	0	0
gen_assertions[2].RstNOn_A	25765195	979	0	0
gen_assertions[3].RstEnOff_A	25765229	11950	0	0
gen_assertions[3].RstEnOn_A	25765229	1022	0	0
gen_assertions[3].RstNOff_A	25765229	11950	0	0
gen_assertions[3].RstNOn_A	25765229	1022	0	0
gen_assertions[4].RstEnOff_A	1625203	20466	0	0
gen_assertions[4].RstEnOn_A	1625203	1073	0	0
gen_assertions[4].RstNOff_A	1625203	20466	0	0
gen_assertions[4].RstNOn_A	1625203	1073	0	0
gen_assertions[5].RstEnOff_A	12882319	13255	0	0
gen_assertions[5].RstEnOn_A	12882319	1151	0	0
gen_assertions[5].RstNOff_A	12882319	13255	0	0
gen_assertions[5].RstNOn_A	12882319	1151	0	0
gen_assertions[6].RstEnOff_A	12882319	13242	0	0
gen_assertions[6].RstEnOn_A	12882319	1137	0	0
gen_assertions[6].RstNOff_A	12882319	13242	0	0
gen_assertions[6].RstNOn_A	12882319	1137	0	0
gen_assertions[7].RstEnOff_A	12882319	13315	0	0
gen_assertions[7].RstEnOn_A	12882319	1210	0	0
gen_assertions[7].RstNOff_A	12882319	13315	0	0
gen_assertions[7].RstNOn_A	12882319	1210	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	12970	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	5	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	354	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1029	0	0
T1	4923	4	0	0
T2	5829	0	0	0
T3	5794	1	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	0	0	0
T7	2282	5	0	0
T8	5854	0	0	0
T9	30659	0	0	0
T10	203486	14	0	0
T25	0	1	0	0
T26	0	13	0	0
T46	0	13	0	0
T59	0	5	0	0
T65	0	1	0	0
T83	0	10	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	12970	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	5	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	354	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1029	0	0
T1	4923	4	0	0
T2	5829	0	0	0
T3	5794	1	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	0	0	0
T7	2282	5	0	0
T8	5854	0	0	0
T9	30659	0	0	0
T10	203486	14	0	0
T25	0	1	0	0
T26	0	13	0	0
T46	0	13	0	0
T59	0	5	0	0
T65	0	1	0	0
T83	0	10	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	11853	0	0
T1	19696	15	0	0
T2	23322	0	0	0
T3	23175	4	0	0
T4	23229	0	0	0
T5	7952	0	0	0
T6	117056	66	0	0
T7	9131	4	0	0
T8	23426	0	0	0
T9	122626	39	0	0
T10	813887	313	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	3	0	0
T25	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	976	0	0
T7	9131	1	0	0
T8	23426	0	0	0
T9	122626	0	0	0
T10	813887	13	0	0
T11	8560	0	0	0
T12	22150	0	0	0
T13	14321	0	0	0
T14	11681	0	0	0
T24	23713	0	0	0
T25	10499	0	0	0
T26	0	15	0	0
T46	0	7	0	0
T52	0	4	0	0
T59	0	6	0	0
T60	0	5	0	0
T61	0	5	0	0
T83	0	4	0	0
T84	0	18	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	11853	0	0
T1	19696	15	0	0
T2	23322	0	0	0
T3	23175	4	0	0
T4	23229	0	0	0
T5	7952	0	0	0
T6	117056	66	0	0
T7	9131	4	0	0
T8	23426	0	0	0
T9	122626	39	0	0
T10	813887	313	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	3	0	0
T25	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	976	0	0
T7	9131	1	0	0
T8	23426	0	0	0
T9	122626	0	0	0
T10	813887	13	0	0
T11	8560	0	0	0
T12	22150	0	0	0
T13	14321	0	0	0
T14	11681	0	0	0
T24	23713	0	0	0
T25	10499	0	0	0
T26	0	15	0	0
T46	0	7	0	0
T52	0	4	0	0
T59	0	6	0	0
T60	0	5	0	0
T61	0	5	0	0
T83	0	4	0	0
T84	0	18	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	11910	0	0
T1	9847	15	0	0
T2	11660	0	0	0
T3	11588	5	0	0
T4	11616	0	0	0
T5	3976	0	0	0
T6	58545	66	0	0
T7	4565	4	0	0
T8	11704	0	0	0
T9	61317	39	0	0
T10	406944	311	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	3	0	0
T25	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	979	0	0
T3	11588	1	0	0
T4	11616	0	0	0
T5	3976	0	0	0
T6	58545	0	0	0
T7	4565	1	0	0
T8	11704	0	0	0
T9	61317	0	0	0
T10	406944	11	0	0
T11	4280	0	0	0
T12	11075	0	0	0
T26	0	13	0	0
T52	0	1	0	0
T59	0	8	0	0
T60	0	6	0	0
T61	0	4	0	0
T65	0	1	0	0
T83	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	11910	0	0
T1	9847	15	0	0
T2	11660	0	0	0
T3	11588	5	0	0
T4	11616	0	0	0
T5	3976	0	0	0
T6	58545	66	0	0
T7	4565	4	0	0
T8	11704	0	0	0
T9	61317	39	0	0
T10	406944	311	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	3	0	0
T25	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	979	0	0
T3	11588	1	0	0
T4	11616	0	0	0
T5	3976	0	0	0
T6	58545	0	0	0
T7	4565	1	0	0
T8	11704	0	0	0
T9	61317	0	0	0
T10	406944	11	0	0
T11	4280	0	0	0
T12	11075	0	0	0
T26	0	13	0	0
T52	0	1	0	0
T59	0	8	0	0
T60	0	6	0	0
T61	0	4	0	0
T65	0	1	0	0
T83	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	11950	0	0
T1	9847	15	0	0
T2	11661	0	0	0
T3	11588	4	0	0
T4	11611	0	0	0
T5	3977	0	0	0
T6	58549	66	0	0
T7	4565	4	0	0
T8	11709	0	0	0
T9	61314	39	0	0
T10	406956	313	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	3	0	0
T25	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	1022	0	0
T10	406956	13	0	0
T11	4280	0	0	0
T12	11076	0	0	0
T13	7163	0	0	0
T14	5841	0	0	0
T24	11852	0	0	0
T25	5247	1	0	0
T26	435494	12	0	0
T27	52339	0	0	0
T28	7911	0	0	0
T59	0	7	0	0
T60	0	6	0	0
T61	0	6	0	0
T84	0	16	0	0
T85	0	3	0	0
T86	0	27	0	0
T87	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	11950	0	0
T1	9847	15	0	0
T2	11661	0	0	0
T3	11588	4	0	0
T4	11611	0	0	0
T5	3977	0	0	0
T6	58549	66	0	0
T7	4565	4	0	0
T8	11709	0	0	0
T9	61314	39	0	0
T10	406956	313	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	3	0	0
T25	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	1022	0	0
T10	406956	13	0	0
T11	4280	0	0	0
T12	11076	0	0	0
T13	7163	0	0	0
T14	5841	0	0	0
T24	11852	0	0	0
T25	5247	1	0	0
T26	435494	12	0	0
T27	52339	0	0	0
T28	7911	0	0	0
T59	0	7	0	0
T60	0	6	0	0
T61	0	6	0	0
T84	0	16	0	0
T85	0	3	0	0
T86	0	27	0	0
T87	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	20466	0	0
T1	614	16	0	0
T2	730	2	0	0
T3	723	6	0	0
T4	728	3	0	0
T5	247	1	0	0
T6	3674	76	0	0
T7	285	6	0	0
T8	734	3	0	0
T9	3895	53	0	0
T10	26127	516	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	1073	0	0
T10	26127	12	0	0
T11	267	0	0	0
T12	690	0	0	0
T13	447	0	0	0
T14	364	1	0	0
T24	743	0	0	0
T25	327	1	0	0
T26	27571	12	0	0
T27	3301	0	0	0
T28	493	0	0	0
T59	0	11	0	0
T60	0	7	0	0
T61	0	7	0	0
T84	0	16	0	0
T85	0	4	0	0
T88	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	20466	0	0
T1	614	16	0	0
T2	730	2	0	0
T3	723	6	0	0
T4	728	3	0	0
T5	247	1	0	0
T6	3674	76	0	0
T7	285	6	0	0
T8	734	3	0	0
T9	3895	53	0	0
T10	26127	516	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	1073	0	0
T10	26127	12	0	0
T11	267	0	0	0
T12	690	0	0	0
T13	447	0	0	0
T14	364	1	0	0
T24	743	0	0	0
T25	327	1	0	0
T26	27571	12	0	0
T27	3301	0	0	0
T28	493	0	0	0
T59	0	11	0	0
T60	0	7	0	0
T61	0	7	0	0
T84	0	16	0	0
T85	0	4	0	0
T88	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	13255	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	4	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	355	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	5	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1151	0	0
T10	203486	16	0	0
T11	2138	0	0	0
T12	5537	0	0	0
T13	3580	0	0	0
T14	2919	0	0	0
T24	5928	0	0	0
T25	2623	1	0	0
T26	217728	15	0	0
T27	26174	0	0	0
T28	3957	0	0	0
T59	0	12	0	0
T60	0	10	0	0
T61	0	10	0	0
T84	0	14	0	0
T85	0	6	0	0
T86	0	30	0	0
T87	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	13255	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	4	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	355	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	5	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1151	0	0
T10	203486	16	0	0
T11	2138	0	0	0
T12	5537	0	0	0
T13	3580	0	0	0
T14	2919	0	0	0
T24	5928	0	0	0
T25	2623	1	0	0
T26	217728	15	0	0
T27	26174	0	0	0
T28	3957	0	0	0
T59	0	12	0	0
T60	0	10	0	0
T61	0	10	0	0
T84	0	14	0	0
T85	0	6	0	0
T86	0	30	0	0
T87	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	13242	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	4	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	355	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1137	0	0
T10	203486	16	0	0
T11	2138	0	0	0
T12	5537	0	0	0
T13	3580	0	0	0
T14	2919	0	0	0
T24	5928	0	0	0
T25	2623	0	0	0
T26	217728	11	0	0
T27	26174	0	0	0
T28	3957	0	0	0
T59	0	13	0	0
T60	0	8	0	0
T61	0	9	0	0
T84	0	17	0	0
T85	0	7	0	0
T86	0	29	0	0
T88	0	1	0	0
T89	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	13242	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	4	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	355	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1137	0	0
T10	203486	16	0	0
T11	2138	0	0	0
T12	5537	0	0	0
T13	3580	0	0	0
T14	2919	0	0	0
T24	5928	0	0	0
T25	2623	0	0	0
T26	217728	11	0	0
T27	26174	0	0	0
T28	3957	0	0	0
T59	0	13	0	0
T60	0	8	0	0
T61	0	9	0	0
T84	0	17	0	0
T85	0	7	0	0
T86	0	29	0	0
T88	0	1	0	0
T89	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	13315	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	4	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	352	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1210	0	0
T10	203486	12	0	0
T11	2138	0	0	0
T12	5537	0	0	0
T13	3580	0	0	0
T14	2919	0	0	0
T24	5928	0	0	0
T25	2623	0	0	0
T26	217728	10	0	0
T27	26174	0	0	0
T28	3957	0	0	0
T59	0	12	0	0
T60	0	10	0	0
T61	0	12	0	0
T84	0	18	0	0
T85	0	7	0	0
T86	0	30	0	0
T87	0	8	0	0
T89	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	13315	0	0
T1	4923	15	0	0
T2	5829	0	0	0
T3	5794	4	0	0
T4	5806	0	0	0
T5	1987	0	0	0
T6	29272	75	0	0
T7	2282	6	0	0
T8	5854	0	0	0
T9	30659	41	0	0
T10	203486	352	0	0
T11	0	2	0	0
T13	0	4	0	0
T14	0	4	0	0
T25	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	1210	0	0
T10	203486	12	0	0
T11	2138	0	0	0
T12	5537	0	0	0
T13	3580	0	0	0
T14	2919	0	0	0
T24	5928	0	0	0
T25	2623	0	0	0
T26	217728	10	0	0
T27	26174	0	0	0
T28	3957	0	0	0
T59	0	12	0	0
T60	0	10	0	0
T61	0	12	0	0
T84	0	18	0	0
T85	0	7	0	0
T86	0	30	0	0
T87	0	8	0	0
T89	0	1	0	0