Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	869626498	476145851	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	869626498	476145851	0	0
T1	332342	222888	0	0
T2	393582	41319	0	0
T3	391070	315691	0	0
T4	391900	41270	0	0
T5	134182	89599	0	0
T6	1975560	653297	0	0
T7	154082	85254	0	0
T8	395106	41762	0	0
T9	2069758	1394494	0	0
T10	13737454	5759999	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53677784	32592189	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	32592189	0	0
T1	20516	17814	0	0
T2	24300	2895	0	0
T3	24139	19933	0	0
T4	24184	2868	0	0
T5	8284	5572	0	0
T6	121924	49695	0	0
T7	9513	6842	0	0
T8	24379	2918	0	0
T9	127760	100499	0	0
T10	847823	463487	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	51528524	31287238	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	31287238	0	0
T1	19696	17101	0	0
T2	23322	2778	0	0
T3	23175	19137	0	0
T4	23229	2751	0	0
T5	7952	5349	0	0
T6	117056	47755	0	0
T7	9131	6569	0	0
T8	23426	2804	0	0
T9	122626	96467	0	0
T10	813887	444922	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765195	15639964	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	15639964	0	0
T1	9847	8550	0	0
T2	11660	1385	0	0
T3	11588	9569	0	0
T4	11616	1373	0	0
T5	3976	2675	0	0
T6	58545	23846	0	0
T7	4565	3284	0	0
T8	11704	1399	0	0
T9	61317	48233	0	0
T10	406944	222380	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	7816774	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	7816774	0	0
T1	4923	4274	0	0
T2	5829	684	0	0
T3	5794	4784	0	0
T4	5806	686	0	0
T5	1987	1336	0	0
T6	29272	11915	0	0
T7	2282	1642	0	0
T8	5854	691	0	0
T9	30659	24113	0	0
T10	203486	111184	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765229	15639914	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	15639914	0	0
T1	9847	8550	0	0
T2	11661	1385	0	0
T3	11588	9569	0	0
T4	11611	1373	0	0
T5	3977	2675	0	0
T6	58549	23879	0	0
T7	4565	3284	0	0
T8	11709	1399	0	0
T9	61314	48224	0	0
T10	406956	222389	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53677784	29233067	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	29233067	0	0
T1	20516	12942	0	0
T2	24300	2789	0	0
T3	24139	19542	0	0
T4	24184	2787	0	0
T5	8284	5564	0	0
T6	121924	39801	0	0
T7	9513	4972	0	0
T8	24379	2815	0	0
T9	127760	83402	0	0
T10	847823	340411	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53677784	28535737	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	28535737	0	0
T1	20516	12751	0	0
T2	24300	2297	0	0
T3	24139	19374	0	0
T4	24184	2296	0	0
T5	8284	5498	0	0
T6	121924	37480	0	0
T7	9513	4857	0	0
T8	24379	2326	0	0
T9	127760	82263	0	0
T10	847823	325780	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53677784	29233335	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	29233335	0	0
T1	20516	12942	0	0
T2	24300	2789	0	0
T3	24139	19542	0	0
T4	24184	2787	0	0
T5	8284	5564	0	0
T6	121924	39864	0	0
T7	9513	4972	0	0
T8	24379	2815	0	0
T9	127760	83402	0	0
T10	847823	340411	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53677784	28536888	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	28536888	0	0
T1	20516	12751	0	0
T2	24300	2297	0	0
T3	24139	19374	0	0
T4	24184	2296	0	0
T5	8284	5498	0	0
T6	121924	37480	0	0
T7	9513	4857	0	0
T8	24379	2326	0	0
T9	127760	82263	0	0
T10	847823	325780	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1625203	867169	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	867169	0	0
T1	614	373	0	0
T2	730	73	0	0
T3	723	580	0	0
T4	728	74	0	0
T5	247	166	0	0
T6	3674	1092	0	0
T7	285	141	0	0
T8	734	74	0	0
T9	3895	2510	0	0
T10	26127	10312	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	51528524	28064224	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	28064224	0	0
T1	19696	12422	0	0
T2	23322	2719	0	0
T3	23175	18761	0	0
T4	23229	2715	0	0
T5	7952	5342	0	0
T6	117056	38299	0	0
T7	9131	4773	0	0
T8	23426	2742	0	0
T9	122626	80053	0	0
T10	813887	326749	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	51528524	27392300	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	27392300	0	0
T1	19696	12238	0	0
T2	23322	2207	0	0
T3	23175	18601	0	0
T4	23229	2203	0	0
T5	7952	5278	0	0
T6	117056	35903	0	0
T7	9131	4661	0	0
T8	23426	2230	0	0
T9	122626	78957	0	0
T10	813887	312701	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765195	14022518	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	14022518	0	0
T1	9847	6203	0	0
T2	11660	1353	0	0
T3	11588	9379	0	0
T4	11616	1357	0	0
T5	3976	2671	0	0
T6	58545	19116	0	0
T7	4565	2383	0	0
T8	11704	1367	0	0
T9	61317	40005	0	0
T10	406944	163125	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765195	13686589	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	13686589	0	0
T1	9847	6111	0	0
T2	11660	1097	0	0
T3	11588	9299	0	0
T4	11616	1101	0	0
T5	3976	2639	0	0
T6	58545	17930	0	0
T7	4565	2327	0	0
T8	11704	1111	0	0
T9	61317	39457	0	0
T10	406944	156101	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6985158	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6985158	0	0
T1	4923	3078	0	0
T2	5829	658	0	0
T3	5794	4682	0	0
T4	5806	660	0	0
T5	1987	1334	0	0
T6	29272	9414	0	0
T7	2282	1182	0	0
T8	5854	665	0	0
T9	30659	19929	0	0
T10	203486	80954	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6817163	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6817163	0	0
T1	4923	3032	0	0
T2	5829	530	0	0
T3	5794	4642	0	0
T4	5806	532	0	0
T5	1987	1318	0	0
T6	29272	8832	0	0
T7	2282	1154	0	0
T8	5854	537	0	0
T9	30659	19655	0	0
T10	203486	77442	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6985158	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6985158	0	0
T1	4923	3078	0	0
T2	5829	658	0	0
T3	5794	4682	0	0
T4	5806	660	0	0
T5	1987	1334	0	0
T6	29272	9414	0	0
T7	2282	1182	0	0
T8	5854	665	0	0
T9	30659	19929	0	0
T10	203486	80954	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6817163	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6817163	0	0
T1	4923	3032	0	0
T2	5829	530	0	0
T3	5794	4642	0	0
T4	5806	532	0	0
T5	1987	1318	0	0
T6	29272	8832	0	0
T7	2282	1154	0	0
T8	5854	537	0	0
T9	30659	19655	0	0
T10	203486	77442	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765229	14022596	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	14022596	0	0
T1	9847	6203	0	0
T2	11661	1353	0	0
T3	11588	9379	0	0
T4	11611	1357	0	0
T5	3977	2671	0	0
T6	58549	19118	0	0
T7	4565	2383	0	0
T8	11709	1367	0	0
T9	61314	39996	0	0
T10	406956	163135	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765229	13686559	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	13686559	0	0
T1	9847	6111	0	0
T2	11661	1097	0	0
T3	11588	9299	0	0
T4	11611	1101	0	0
T5	3977	2639	0	0
T6	58549	17932	0	0
T7	4565	2327	0	0
T8	11709	1111	0	0
T9	61314	39448	0	0
T10	406956	156111	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53677784	28257152	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53677784	28257152	0	0
T1	20516	12350	0	0
T2	24300	2297	0	0
T3	24139	19208	0	0
T4	24184	2296	0	0
T5	8284	5498	0	0
T6	121924	35660	0	0
T7	9513	4736	0	0
T8	24379	2326	0	0
T9	127760	81255	0	0
T10	847823	318324	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6918487	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6918487	0	0
T1	4923	2982	0	0
T2	5829	668	0	0
T3	5794	4642	0	0
T4	5806	670	0	0
T5	1987	1334	0	0
T6	29272	8977	0	0
T7	2282	1153	0	0
T8	5854	675	0	0
T9	30659	19688	0	0
T10	203486	79165	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6679075	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6679075	0	0
T1	4923	3009	0	0
T2	5829	540	0	0
T3	5794	4469	0	0
T4	5806	542	0	0
T5	1987	1318	0	0
T6	29272	8832	0	0
T7	2282	1124	0	0
T8	5854	547	0	0
T9	30659	19655	0	0
T10	203486	76836	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	51528524	26822756	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51528524	26822756	0	0
T1	19696	12238	0	0
T2	23322	2207	0	0
T3	23175	18601	0	0
T4	23229	2203	0	0
T5	7952	5278	0	0
T6	117056	35927	0	0
T7	9131	4639	0	0
T8	23426	2230	0	0
T9	122626	78957	0	0
T10	813887	308132	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765195	13400532	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765195	13400532	0	0
T1	9847	6111	0	0
T2	11660	1097	0	0
T3	11588	9008	0	0
T4	11616	1101	0	0
T5	3976	2639	0	0
T6	58545	17920	0	0
T7	4565	2319	0	0
T8	11704	1111	0	0
T9	61317	39457	0	0
T10	406944	153993	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	25765229	13384872	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25765229	13384872	0	0
T1	9847	6111	0	0
T2	11661	1097	0	0
T3	11588	9299	0	0
T4	11611	1101	0	0
T5	3977	2639	0	0
T6	58549	17930	0	0
T7	4565	2327	0	0
T8	11709	1111	0	0
T9	61314	39448	0	0
T10	406956	153676	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1625203	827498	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	827498	0	0
T1	614	367	0	0
T2	730	57	0	0
T3	723	574	0	0
T4	728	58	0	0
T5	247	164	0	0
T6	3674	1017	0	0
T7	285	138	0	0
T8	734	58	0	0
T9	3895	2469	0	0
T10	26127	9822	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6666252	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6666252	0	0
T1	4923	3032	0	0
T2	5829	540	0	0
T3	5794	4642	0	0
T4	5806	542	0	0
T5	1987	1318	0	0
T6	29272	8820	0	0
T7	2282	1154	0	0
T8	5854	547	0	0
T9	30659	19655	0	0
T10	203486	76145	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6674365	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6674365	0	0
T1	4923	3032	0	0
T2	5829	540	0	0
T3	5794	4642	0	0
T4	5806	542	0	0
T5	1987	1318	0	0
T6	29272	8832	0	0
T7	2282	1154	0	0
T8	5854	547	0	0
T9	30659	19655	0	0
T10	203486	76169	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	12882319	6680528	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12882319	6680528	0	0
T1	4923	3032	0	0
T2	5829	540	0	0
T3	5794	4642	0	0
T4	5806	542	0	0
T5	1987	1318	0	0
T6	29272	8815	0	0
T7	2282	1154	0	0
T8	5854	547	0	0
T9	30659	19655	0	0
T10	203486	77011	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1625203	995298	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	995298	0	0
T1	614	535	0	0
T2	730	89	0	0
T3	723	599	0	0
T4	728	90	0	0
T5	247	168	0	0
T6	3674	1512	0	0
T7	285	206	0	0
T8	734	90	0	0
T9	3895	3082	0	0
T10	26127	14655	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1625203	977333	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1625203	977333	0	0
T1	614	533	0	0
T2	730	73	0	0
T3	723	595	0	0
T4	728	74	0	0
T5	247	166	0	0
T6	3674	1458	0	0
T7	285	204	0	0
T8	734	74	0	0
T9	3895	3058	0	0
T10	26127	14301	0	0