Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12250599	7904	0	0
alert_regwen_rd_A	12250599	5628	0	0
cpu_regwen_rd_A	12250599	5831	0	0
sw_rst_ctrl_n_0_rd_A	12250599	10930	0	0
sw_rst_ctrl_n_1_rd_A	12250599	11122	0	0
sw_rst_ctrl_n_2_rd_A	12250599	11116	0	0
sw_rst_ctrl_n_3_rd_A	12250599	10903	0	0
sw_rst_ctrl_n_4_rd_A	12250599	11366	0	0
sw_rst_ctrl_n_5_rd_A	12250599	11081	0	0
sw_rst_ctrl_n_6_rd_A	12250599	11218	0	0
sw_rst_ctrl_n_7_rd_A	12250599	11068	0	0
sw_rst_regwen_0_rd_A	12250599	6387	0	0
sw_rst_regwen_1_rd_A	12250599	6213	0	0
sw_rst_regwen_2_rd_A	12250599	6491	0	0
sw_rst_regwen_3_rd_A	12250599	6509	0	0
sw_rst_regwen_4_rd_A	12250599	6246	0	0
sw_rst_regwen_5_rd_A	12250599	6375	0	0
sw_rst_regwen_6_rd_A	12250599	6537	0	0
sw_rst_regwen_7_rd_A	12250599	6454	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	7904	0	0
T62	2598	6	0	0
T66	5027	108	0	0
T67	8120	487	0	0
T68	11837	1	0	0
T91	2202	8	0	0
T92	2933	49	0	0
T93	5874	315	0	0
T94	13217	707	0	0
T95	21639	1	0	0
T97	4922	24	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	5628	0	0
T57	43622	101	0	0
T60	7190	0	0	0
T61	9937	0	0	0
T100	13797	0	0	0
T102	0	46	0	0
T103	0	78	0	0
T104	0	57	0	0
T106	0	73	0	0
T107	0	154	0	0
T116	0	43	0	0
T135	0	330	0	0
T136	0	255	0	0
T137	0	32	0	0
T138	3917	0	0	0
T139	1429	0	0	0
T140	5487	0	0	0
T141	3095	0	0	0
T142	1427	0	0	0
T143	2280	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	5831	0	0
T57	43622	71	0	0
T60	7190	0	0	0
T61	9937	0	0	0
T100	13797	0	0	0
T102	0	28	0	0
T103	0	70	0	0
T104	0	66	0	0
T106	0	55	0	0
T107	0	114	0	0
T116	0	49	0	0
T135	0	367	0	0
T136	0	295	0	0
T137	0	55	0	0
T138	3917	0	0	0
T139	1429	0	0	0
T140	5487	0	0	0
T141	3095	0	0	0
T142	1427	0	0	0
T143	2280	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	10930	0	0
T3	5606	16	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	4	0	0
T12	5422	0	0	0
T57	0	97	0	0
T61	0	176	0	0
T65	0	15	0	0
T88	0	15	0	0
T108	0	44	0	0
T112	0	164	0	0
T144	0	55	0	0
T145	0	23	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	11122	0	0
T3	5606	25	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	7	0	0
T12	5422	0	0	0
T57	0	76	0	0
T61	0	176	0	0
T65	0	12	0	0
T88	0	13	0	0
T108	0	49	0	0
T112	0	223	0	0
T144	0	68	0	0
T145	0	11	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	11116	0	0
T3	5606	10	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	7	0	0
T12	5422	0	0	0
T57	0	109	0	0
T61	0	171	0	0
T88	0	17	0	0
T108	0	52	0	0
T112	0	193	0	0
T113	0	6	0	0
T144	0	71	0	0
T145	0	12	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	10903	0	0
T3	5606	18	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	3	0	0
T12	5422	0	0	0
T57	0	92	0	0
T61	0	166	0	0
T65	0	8	0	0
T88	0	11	0	0
T108	0	52	0	0
T112	0	195	0	0
T144	0	52	0	0
T145	0	10	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	11366	0	0
T3	5606	23	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	6	0	0
T12	5422	0	0	0
T57	0	76	0	0
T61	0	187	0	0
T65	0	19	0	0
T88	0	28	0	0
T108	0	45	0	0
T112	0	162	0	0
T144	0	59	0	0
T145	0	12	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	11081	0	0
T3	5606	14	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	13	0	0
T12	5422	0	0	0
T57	0	80	0	0
T61	0	170	0	0
T65	0	7	0	0
T88	0	17	0	0
T108	0	55	0	0
T112	0	221	0	0
T144	0	63	0	0
T145	0	15	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	11218	0	0
T3	5606	12	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	12	0	0
T12	5422	0	0	0
T57	0	73	0	0
T61	0	136	0	0
T88	0	20	0	0
T102	0	43	0	0
T108	0	58	0	0
T112	0	221	0	0
T144	0	72	0	0
T145	0	17	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	11068	0	0
T3	5606	19	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	8	0	0
T12	5422	0	0	0
T57	0	89	0	0
T61	0	140	0	0
T65	0	6	0	0
T88	0	6	0	0
T108	0	59	0	0
T112	0	181	0	0
T144	0	76	0	0
T145	0	21	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6387	0	0
T3	5606	1	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	75	0	0
T61	0	25	0	0
T88	0	17	0	0
T102	0	61	0	0
T112	0	27	0	0
T113	0	9	0	0
T145	0	8	0	0
T146	0	23	0	0
T147	0	26	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6213	0	0
T3	5606	7	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	80	0	0
T61	0	32	0	0
T65	0	13	0	0
T102	0	52	0	0
T112	0	23	0	0
T113	0	3	0	0
T145	0	5	0	0
T146	0	18	0	0
T147	0	28	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6491	0	0
T3	5606	9	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	72	0	0
T61	0	33	0	0
T65	0	1	0	0
T102	0	42	0	0
T112	0	28	0	0
T113	0	5	0	0
T145	0	7	0	0
T146	0	32	0	0
T147	0	36	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6509	0	0
T3	5606	4	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	85	0	0
T61	0	31	0	0
T65	0	7	0	0
T88	0	7	0	0
T102	0	55	0	0
T112	0	25	0	0
T113	0	6	0	0
T145	0	5	0	0
T146	0	16	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6246	0	0
T3	5606	7	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	98	0	0
T61	0	57	0	0
T88	0	8	0	0
T102	0	59	0	0
T112	0	33	0	0
T113	0	2	0	0
T145	0	5	0	0
T146	0	22	0	0
T147	0	38	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6375	0	0
T3	5606	6	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	77	0	0
T61	0	23	0	0
T65	0	5	0	0
T88	0	2	0	0
T102	0	34	0	0
T112	0	41	0	0
T145	0	8	0	0
T146	0	7	0	0
T147	0	29	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6537	0	0
T3	5606	4	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	58	0	0
T61	0	27	0	0
T65	0	3	0	0
T88	0	7	0	0
T102	0	43	0	0
T112	0	33	0	0
T113	0	7	0	0
T145	0	2	0	0
T146	0	15	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12250599	6454	0	0
T3	5606	5	0	0
T4	5452	0	0	0
T5	1921	0	0	0
T6	26009	0	0	0
T7	1868	0	0	0
T8	5309	0	0	0
T9	26014	0	0	0
T10	158172	0	0	0
T11	1986	0	0	0
T12	5422	0	0	0
T57	0	62	0	0
T61	0	27	0	0
T65	0	4	0	0
T88	0	6	0	0
T102	0	32	0	0
T112	0	35	0	0
T145	0	9	0	0
T146	0	27	0	0
T147	0	25	0	0