Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	616451	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

368916

1

T2

3470

T3

386

T4

1103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	526258	1			T2	5264		T3	515		T4	1500
values[0x0]	228689	1			T2	1999		T3	249		T4	870
values[0x1]	230420	1			T2	2086		T3	220		T4	830

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	517023	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

468344

1

T2

4393

T3

476

T4

1437

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3258	1			T2	155		T4	26		T5	8
valid_sources[0x01]	3167	1			T4	13		T5	10		T6	3
valid_sources[0x02]	3927	1			T4	17		T5	22		T6	3
valid_sources[0x03]	3262	1			T2	140		T4	11		T5	6
valid_sources[0x04]	3360	1			T4	16		T6	1		T12	14
valid_sources[0x05]	4250	1			T3	11		T4	9		T5	13
valid_sources[0x06]	3530	1			T4	12		T5	5		T12	13
valid_sources[0x07]	3314	1			T2	70		T4	14		T5	8
valid_sources[0x08]	3450	1			T4	9		T5	15		T6	2
valid_sources[0x09]	2926	1			T4	7		T5	9		T12	16
valid_sources[0x0a]	4497	1			T4	8		T5	16		T6	7
valid_sources[0x0b]	3305	1			T3	6		T4	11		T12	4
valid_sources[0x0c]	6254	1			T3	4		T4	18		T5	7
valid_sources[0x0d]	4464	1			T4	9		T5	13		T12	10
valid_sources[0x0e]	2883	1			T4	24		T5	26		T12	9
valid_sources[0x0f]	2977	1			T3	4		T4	5		T5	13
valid_sources[0x10]	3157	1			T2	113		T4	17		T5	32
valid_sources[0x11]	2851	1			T4	11		T5	5		T6	7
valid_sources[0x12]	4026	1			T3	13		T4	14		T5	10
valid_sources[0x13]	4421	1			T2	872		T4	7		T5	24
valid_sources[0x14]	3588	1			T4	15		T6	5		T12	6
valid_sources[0x15]	3018	1			T4	10		T5	16		T6	1
valid_sources[0x16]	5443	1			T2	13		T4	16		T5	15
valid_sources[0x17]	4086	1			T4	10		T5	5		T12	14
valid_sources[0x18]	3974	1			T4	12		T5	3		T12	16
valid_sources[0x19]	3385	1			T2	155		T3	10		T4	9
valid_sources[0x1a]	4130	1			T4	18		T5	26		T12	5
valid_sources[0x1b]	2871	1			T2	70		T4	13		T5	20
valid_sources[0x1c]	3992	1			T4	13		T5	2		T12	15
valid_sources[0x1d]	3389	1			T2	70		T4	7		T5	13
valid_sources[0x1e]	3046	1			T4	16		T5	20		T6	2
valid_sources[0x1f]	2888	1			T4	5		T5	14		T6	1
valid_sources[0x20]	3892	1			T4	10		T5	8		T12	1
valid_sources[0x21]	3948	1			T3	5		T4	10		T5	6
valid_sources[0x22]	3609	1			T4	7		T5	4		T12	6
valid_sources[0x23]	3952	1			T3	17		T4	12		T5	17
valid_sources[0x24]	4029	1			T3	6		T4	8		T5	15
valid_sources[0x25]	3784	1			T2	113		T4	14		T5	4
valid_sources[0x26]	4187	1			T3	5		T4	15		T5	11
valid_sources[0x27]	4014	1			T2	70		T4	4		T6	1
valid_sources[0x28]	4151	1			T4	11		T5	12		T6	2
valid_sources[0x29]	3731	1			T4	15		T5	6		T12	24
valid_sources[0x2a]	2892	1			T4	13		T5	21		T12	7
valid_sources[0x2b]	3383	1			T3	1		T4	12		T5	15
valid_sources[0x2c]	4716	1			T4	3		T5	8		T6	2
valid_sources[0x2d]	3295	1			T4	9		T5	11		T12	4
valid_sources[0x2e]	3213	1			T3	2		T4	6		T5	13
valid_sources[0x2f]	2935	1			T3	16		T4	10		T5	11
valid_sources[0x30]	3165	1			T3	4		T4	9		T5	4
valid_sources[0x31]	4218	1			T2	155		T3	1		T4	18
valid_sources[0x32]	3435	1			T4	11		T5	6		T13	11
valid_sources[0x33]	4284	1			T4	11		T5	11		T9	1
valid_sources[0x34]	3531	1			T4	11		T5	13		T6	2
valid_sources[0x35]	3759	1			T4	17		T5	6		T6	8
valid_sources[0x36]	3677	1			T2	98		T3	23		T4	11
valid_sources[0x37]	3427	1			T4	15		T5	14		T12	27
valid_sources[0x38]	3438	1			T4	17		T5	17		T6	9
valid_sources[0x39]	4103	1			T3	13		T4	7		T5	13
valid_sources[0x3a]	3785	1			T2	70		T4	5		T5	22
valid_sources[0x3b]	3670	1			T2	70		T4	24		T5	18
valid_sources[0x3c]	3666	1			T4	24		T5	8		T6	3
valid_sources[0x3d]	3698	1			T2	155		T3	10		T4	16
valid_sources[0x3e]	3301	1			T3	6		T4	18		T5	5
valid_sources[0x3f]	4527	1			T3	1		T4	6		T5	10
valid_sources[0x40]	7343	1			T3	6		T4	3		T5	3
valid_sources[0x41]	4016	1			T4	14		T5	28		T9	1
valid_sources[0x42]	3390	1			T4	26		T5	6		T6	1
valid_sources[0x43]	3341	1			T4	23		T5	27		T10	1
valid_sources[0x44]	3250	1			T3	1		T4	12		T5	12
valid_sources[0x45]	3486	1			T4	10		T5	13		T6	2
valid_sources[0x46]	3517	1			T3	16		T4	14		T5	7
valid_sources[0x47]	3512	1			T3	20		T4	21		T5	11
valid_sources[0x48]	2772	1			T4	6		T5	9		T12	16
valid_sources[0x49]	4577	1			T4	16		T5	7		T6	3
valid_sources[0x4a]	2692	1			T3	3		T4	15		T5	12
valid_sources[0x4b]	3033	1			T4	10		T5	2		T6	2
valid_sources[0x4c]	2971	1			T3	1		T4	14		T5	44
valid_sources[0x4d]	3326	1			T4	22		T5	12		T6	1
valid_sources[0x4e]	4191	1			T3	4		T4	13		T5	4
valid_sources[0x4f]	3370	1			T4	16		T5	19		T12	21
valid_sources[0x50]	4057	1			T4	7		T5	10		T6	2
valid_sources[0x51]	3447	1			T4	7		T5	26		T12	5
valid_sources[0x52]	3927	1			T2	70		T4	18		T5	18
valid_sources[0x53]	3916	1			T4	10		T5	17		T6	1
valid_sources[0x54]	3688	1			T2	225		T3	33		T4	17
valid_sources[0x55]	3355	1			T3	7		T4	10		T5	20
valid_sources[0x56]	3304	1			T3	14		T4	10		T5	2
valid_sources[0x57]	3542	1			T4	7		T5	26		T6	1
valid_sources[0x58]	3946	1			T4	18		T5	9		T6	1
valid_sources[0x59]	2980	1			T2	69		T4	18		T12	5
valid_sources[0x5a]	4090	1			T2	185		T4	15		T5	15
valid_sources[0x5b]	7280	1			T3	4		T4	7		T5	1
valid_sources[0x5c]	3690	1			T3	3		T4	8		T12	6
valid_sources[0x5d]	3915	1			T4	6		T5	9		T12	4
valid_sources[0x5e]	3675	1			T2	112		T3	5		T4	17
valid_sources[0x5f]	7103	1			T4	12		T5	2		T6	1
valid_sources[0x60]	3588	1			T3	15		T4	15		T5	9
valid_sources[0x61]	4329	1			T4	16		T5	28		T6	4
valid_sources[0x62]	3075	1			T4	21		T5	5		T10	2
valid_sources[0x63]	3441	1			T4	16		T5	7		T6	1
valid_sources[0x64]	3638	1			T3	1		T4	13		T5	2
valid_sources[0x65]	3091	1			T2	154		T3	18		T4	2
valid_sources[0x66]	4951	1			T4	10		T5	22		T6	7
valid_sources[0x67]	3118	1			T3	3		T4	15		T5	2
valid_sources[0x68]	3679	1			T2	550		T4	13		T5	19
valid_sources[0x69]	3307	1			T4	10		T5	3		T6	1
valid_sources[0x6a]	3074	1			T3	23		T4	13		T5	13
valid_sources[0x6b]	6502	1			T3	22		T4	11		T5	10
valid_sources[0x6c]	3471	1			T4	19		T5	2		T6	3
valid_sources[0x6d]	3124	1			T3	4		T4	10		T5	17
valid_sources[0x6e]	3621	1			T2	197		T4	12		T5	6
valid_sources[0x6f]	3674	1			T4	8		T5	14		T9	1
valid_sources[0x70]	3405	1			T4	14		T5	42		T6	4
valid_sources[0x71]	4110	1			T2	155		T4	10		T5	11
valid_sources[0x72]	2994	1			T4	13		T5	5		T6	1
valid_sources[0x73]	3040	1			T4	19		T5	5		T6	2
valid_sources[0x74]	3747	1			T4	27		T5	17		T12	6
valid_sources[0x75]	3381	1			T3	1		T4	12		T5	7
valid_sources[0x76]	4613	1			T3	14		T4	6		T5	11
valid_sources[0x77]	3215	1			T4	14		T5	24		T12	15
valid_sources[0x78]	4048	1			T4	17		T5	16		T6	4
valid_sources[0x79]	6309	1			T3	14		T4	11		T5	4
valid_sources[0x7a]	3637	1			T3	2		T4	6		T5	37
valid_sources[0x7b]	6957	1			T3	1		T4	4		T5	27
valid_sources[0x7c]	3335	1			T3	1		T4	12		T6	1
valid_sources[0x7d]	4281	1			T3	15		T4	8		T5	1
valid_sources[0x7e]	6630	1			T3	7		T4	13		T12	12
valid_sources[0x7f]	4369	1			T3	3		T4	5		T5	10
valid_sources[0x80]	3835	1			T3	6		T4	10		T5	36

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

245716

1

T2

2439

T3

263

T4

667

values[0x0]

all_enables

biggest_size

80211

1

T2

676

T3

78

T4

290

values[0x1]

all_enables

biggest_size

42989

1

T2

355

T3

45

T4

146