Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T12
1	0	Covered	T2,T12,T14

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53940794	9188	0	0
CascadeEffAonToRstPorAboveRise_A	53940794	9188	0	0
CascadeEffAonToRstPorIoAboveFall_A	51781144	9188	0	0
CascadeEffAonToRstPorIoAboveRise_A	51781144	9188	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25891471	9188	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25891471	9188	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12945437	9188	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12945437	9188	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25891312	9188	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25891312	9188	0	0
CascadeLcToLcAboveFall_A	53940794	22309	0	0
CascadeLcToLcAboveRise_A	53940794	22309	0	0
CascadeLcToLcAonAboveFall_A	1635037	22309	0	0
CascadeLcToLcAonAboveRise_A	1635037	22309	0	0
CascadeLcToLcShadowedAboveFall_A	53940794	22309	0	0
CascadeLcToLcShadowedAboveRise_A	53940794	22309	0	0
CascadePorToAonAboveFall_A	1635037	7415	0	0
CascadeSysToSysAboveFall_A	53940794	22309	0	0
CascadeSysToSysAboveRise_A	53940794	22309	0	0
ScanRstToAonRise_A	1635037	212	0	0
StablePorToAonRise_A	1635037	9188	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11442180	22309	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11442180	22309	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11442180	22309	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11442180	22309	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12945437	22309	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12945437	22309	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11442180	22309	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11442180	22309	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11442180	22309	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11442180	22309	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	9188	0	0
T1	24353	8	0	0
T2	496514	67	0	0
T3	50701	1	0	0
T4	122332	27	0	0
T5	122150	27	0	0
T6	12522	2	0	0
T7	10270	2	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	9188	0	0
T1	24353	8	0	0
T2	496514	67	0	0
T3	50701	1	0	0
T4	122332	27	0	0
T5	122150	27	0	0
T6	12522	2	0	0
T7	10270	2	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51781144	9188	0	0
T1	23376	8	0	0
T2	476625	67	0	0
T3	48671	1	0	0
T4	117428	27	0	0
T5	117298	27	0	0
T6	12021	2	0	0
T7	9857	2	0	0
T8	24946	1	0	0
T9	6869	1	0	0
T10	7357	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51781144	9188	0	0
T1	23376	8	0	0
T2	476625	67	0	0
T3	48671	1	0	0
T4	117428	27	0	0
T5	117298	27	0	0
T6	12021	2	0	0
T7	9857	2	0	0
T8	24946	1	0	0
T9	6869	1	0	0
T10	7357	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891471	9188	0	0
T1	11684	8	0	0
T2	238354	67	0	0
T3	24336	1	0	0
T4	58710	27	0	0
T5	58633	27	0	0
T6	6011	2	0	0
T7	4929	2	0	0
T8	12473	1	0	0
T9	3433	1	0	0
T10	3678	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891471	9188	0	0
T1	11684	8	0	0
T2	238354	67	0	0
T3	24336	1	0	0
T4	58710	27	0	0
T5	58633	27	0	0
T6	6011	2	0	0
T7	4929	2	0	0
T8	12473	1	0	0
T9	3433	1	0	0
T10	3678	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	9188	0	0
T1	5843	8	0	0
T2	119167	67	0	0
T3	12167	1	0	0
T4	29357	27	0	0
T5	29323	27	0	0
T6	3005	2	0	0
T7	2463	2	0	0
T8	6234	1	0	0
T9	1717	1	0	0
T10	1837	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	9188	0	0
T1	5843	8	0	0
T2	119167	67	0	0
T3	12167	1	0	0
T4	29357	27	0	0
T5	29323	27	0	0
T6	3005	2	0	0
T7	2463	2	0	0
T8	6234	1	0	0
T9	1717	1	0	0
T10	1837	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891312	9188	0	0
T1	11688	8	0	0
T2	238332	67	0	0
T3	24336	1	0	0
T4	58725	27	0	0
T5	58638	27	0	0
T6	6009	2	0	0
T7	4928	2	0	0
T8	12473	1	0	0
T9	3433	1	0	0
T10	3678	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891312	9188	0	0
T1	11688	8	0	0
T2	238332	67	0	0
T3	24336	1	0	0
T4	58725	27	0	0
T5	58638	27	0	0
T6	6009	2	0	0
T7	4928	2	0	0
T8	12473	1	0	0
T9	3433	1	0	0
T10	3678	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	22309	0	0
T1	24353	8	0	0
T2	496514	176	0	0
T3	50701	1	0	0
T4	122332	102	0	0
T5	122150	102	0	0
T6	12522	6	0	0
T7	10270	6	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	22309	0	0
T1	24353	8	0	0
T2	496514	176	0	0
T3	50701	1	0	0
T4	122332	102	0	0
T5	122150	102	0	0
T6	12522	6	0	0
T7	10270	6	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	22309	0	0
T1	732	8	0	0
T2	15045	176	0	0
T3	1520	1	0	0
T4	3683	102	0	0
T5	3679	102	0	0
T6	374	6	0	0
T7	306	6	0	0
T8	777	1	0	0
T9	214	1	0	0
T10	230	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	22309	0	0
T1	732	8	0	0
T2	15045	176	0	0
T3	1520	1	0	0
T4	3683	102	0	0
T5	3679	102	0	0
T6	374	6	0	0
T7	306	6	0	0
T8	777	1	0	0
T9	214	1	0	0
T10	230	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	22309	0	0
T1	24353	8	0	0
T2	496514	176	0	0
T3	50701	1	0	0
T4	122332	102	0	0
T5	122150	102	0	0
T6	12522	6	0	0
T7	10270	6	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	22309	0	0
T1	24353	8	0	0
T2	496514	176	0	0
T3	50701	1	0	0
T4	122332	102	0	0
T5	122150	102	0	0
T6	12522	6	0	0
T7	10270	6	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	7415	0	0
T1	732	8	0	0
T2	15045	33	0	0
T3	1520	1	0	0
T4	3683	27	0	0
T5	3679	27	0	0
T6	374	1	0	0
T7	306	1	0	0
T8	777	1	0	0
T9	214	1	0	0
T10	230	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	22309	0	0
T1	24353	8	0	0
T2	496514	176	0	0
T3	50701	1	0	0
T4	122332	102	0	0
T5	122150	102	0	0
T6	12522	6	0	0
T7	10270	6	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53940794	22309	0	0
T1	24353	8	0	0
T2	496514	176	0	0
T3	50701	1	0	0
T4	122332	102	0	0
T5	122150	102	0	0
T6	12522	6	0	0
T7	10270	6	0	0
T8	25986	1	0	0
T9	7155	1	0	0
T10	7664	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	212	0	0
T2	15045	1	0	0
T3	1520	0	0	0
T4	3683	0	0	0
T5	3679	0	0	0
T6	374	0	0	0
T7	306	0	0	0
T8	777	0	0	0
T9	214	0	0	0
T10	230	0	0	0
T11	504	0	0	0
T12	0	1	0	0
T42	0	7	0	0
T83	0	1	0	0
T84	0	4	0	0
T86	0	3	0	0
T118	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	9188	0	0
T1	732	8	0	0
T2	15045	67	0	0
T3	1520	1	0	0
T4	3683	27	0	0
T5	3679	27	0	0
T6	374	2	0	0
T7	306	2	0	0
T8	777	1	0	0
T9	214	1	0	0
T10	230	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	22309	0	0
T1	5843	8	0	0
T2	119167	176	0	0
T3	12167	1	0	0
T4	29357	102	0	0
T5	29323	102	0	0
T6	3005	6	0	0
T7	2463	6	0	0
T8	6234	1	0	0
T9	1717	1	0	0
T10	1837	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	22309	0	0
T1	5843	8	0	0
T2	119167	176	0	0
T3	12167	1	0	0
T4	29357	102	0	0
T5	29323	102	0	0
T6	3005	6	0	0
T7	2463	6	0	0
T8	6234	1	0	0
T9	1717	1	0	0
T10	1837	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11442180	22309	0	0
T1	5489	8	0	0
T2	103362	176	0	0
T3	12077	1	0	0
T4	26059	102	0	0
T5	26366	102	0	0
T6	2810	6	0	0
T7	2270	6	0	0
T8	6169	1	0	0
T9	1674	1	0	0
T10	1820	1	0	0