Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12945437	13925	0	0
gen_assertions[0].RstEnOn_A	12945437	978	0	0
gen_assertions[0].RstNOff_A	12945437	13925	0	0
gen_assertions[0].RstNOn_A	12945437	978	0	0
gen_assertions[1].RstEnOff_A	51781144	12588	0	0
gen_assertions[1].RstEnOn_A	51781144	955	0	0
gen_assertions[1].RstNOff_A	51781144	12588	0	0
gen_assertions[1].RstNOn_A	51781144	955	0	0
gen_assertions[2].RstEnOff_A	25891471	12634	0	0
gen_assertions[2].RstEnOn_A	25891471	921	0	0
gen_assertions[2].RstNOff_A	25891471	12634	0	0
gen_assertions[2].RstNOn_A	25891471	921	0	0
gen_assertions[3].RstEnOff_A	25891312	12692	0	0
gen_assertions[3].RstEnOn_A	25891312	975	0	0
gen_assertions[3].RstNOff_A	25891312	12692	0	0
gen_assertions[3].RstNOn_A	25891312	975	0	0
gen_assertions[4].RstEnOff_A	1635037	21878	0	0
gen_assertions[4].RstEnOn_A	1635037	1024	0	0
gen_assertions[4].RstNOff_A	1635037	21878	0	0
gen_assertions[4].RstNOn_A	1635037	1024	0	0
gen_assertions[5].RstEnOff_A	12945437	14157	0	0
gen_assertions[5].RstEnOn_A	12945437	1063	0	0
gen_assertions[5].RstNOff_A	12945437	14157	0	0
gen_assertions[5].RstNOn_A	12945437	1063	0	0
gen_assertions[6].RstEnOff_A	12945437	14217	0	0
gen_assertions[6].RstEnOn_A	12945437	1137	0	0
gen_assertions[6].RstNOff_A	12945437	14217	0	0
gen_assertions[6].RstNOn_A	12945437	1137	0	0
gen_assertions[7].RstEnOff_A	12945437	14274	0	0
gen_assertions[7].RstEnOn_A	12945437	1188	0	0
gen_assertions[7].RstNOff_A	12945437	14274	0	0
gen_assertions[7].RstNOn_A	12945437	1188	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	13925	0	0
T2	119167	116	0	0
T3	12167	6	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	2	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	978	0	0
T2	119167	7	0	0
T3	12167	6	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	2	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T26	0	7	0	0
T28	0	1	0	0
T42	0	11	0	0
T45	0	9	0	0
T46	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	13925	0	0
T2	119167	116	0	0
T3	12167	6	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	2	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	978	0	0
T2	119167	7	0	0
T3	12167	6	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	2	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T14	0	1	0	0
T15	0	2	0	0
T26	0	7	0	0
T28	0	1	0	0
T42	0	11	0	0
T45	0	9	0	0
T46	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51781144	12588	0	0
T2	476625	100	0	0
T3	48671	8	0	0
T4	117428	70	0	0
T5	117298	64	0	0
T6	12021	2	0	0
T7	9857	3	0	0
T8	24946	3	0	0
T9	6869	0	0	0
T10	7357	0	0	0
T11	16178	4	0	0
T12	0	31	0	0
T13	0	64	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51781144	955	0	0
T2	476625	8	0	0
T3	48671	8	0	0
T4	117428	0	0	0
T5	117298	0	0	0
T6	12021	0	0	0
T7	9857	0	0	0
T8	24946	3	0	0
T9	6869	0	0	0
T10	7357	0	0	0
T11	16178	0	0	0
T15	0	1	0	0
T26	0	9	0	0
T42	0	12	0	0
T45	0	8	0	0
T46	0	7	0	0
T81	0	7	0	0
T82	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51781144	12588	0	0
T2	476625	100	0	0
T3	48671	8	0	0
T4	117428	70	0	0
T5	117298	64	0	0
T6	12021	2	0	0
T7	9857	3	0	0
T8	24946	3	0	0
T9	6869	0	0	0
T10	7357	0	0	0
T11	16178	4	0	0
T12	0	31	0	0
T13	0	64	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51781144	955	0	0
T2	476625	8	0	0
T3	48671	8	0	0
T4	117428	0	0	0
T5	117298	0	0	0
T6	12021	0	0	0
T7	9857	0	0	0
T8	24946	3	0	0
T9	6869	0	0	0
T10	7357	0	0	0
T11	16178	0	0	0
T15	0	1	0	0
T26	0	9	0	0
T42	0	12	0	0
T45	0	8	0	0
T46	0	7	0	0
T81	0	7	0	0
T82	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891471	12634	0	0
T2	238354	99	0	0
T3	24336	8	0	0
T4	58710	70	0	0
T5	58633	64	0	0
T6	6011	3	0	0
T7	4929	3	0	0
T8	12473	3	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	4	0	0
T12	0	31	0	0
T13	0	64	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891471	921	0	0
T2	238354	7	0	0
T3	24336	8	0	0
T4	58710	0	0	0
T5	58633	0	0	0
T6	6011	1	0	0
T7	4929	0	0	0
T8	12473	3	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	0	0	0
T14	0	1	0	0
T26	0	10	0	0
T42	0	9	0	0
T45	0	1	0	0
T46	0	8	0	0
T81	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891471	12634	0	0
T2	238354	99	0	0
T3	24336	8	0	0
T4	58710	70	0	0
T5	58633	64	0	0
T6	6011	3	0	0
T7	4929	3	0	0
T8	12473	3	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	4	0	0
T12	0	31	0	0
T13	0	64	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891471	921	0	0
T2	238354	7	0	0
T3	24336	8	0	0
T4	58710	0	0	0
T5	58633	0	0	0
T6	6011	1	0	0
T7	4929	0	0	0
T8	12473	3	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	0	0	0
T14	0	1	0	0
T26	0	10	0	0
T42	0	9	0	0
T45	0	1	0	0
T46	0	8	0	0
T81	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891312	12692	0	0
T2	238332	98	0	0
T3	24336	8	0	0
T4	58725	70	0	0
T5	58638	64	0	0
T6	6009	2	0	0
T7	4928	3	0	0
T8	12473	4	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	4	0	0
T12	0	31	0	0
T13	0	64	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891312	975	0	0
T2	238332	6	0	0
T3	24336	8	0	0
T4	58725	0	0	0
T5	58638	0	0	0
T6	6009	0	0	0
T7	4928	0	0	0
T8	12473	4	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	0	0	0
T26	0	10	0	0
T42	0	13	0	0
T46	0	9	0	0
T81	0	10	0	0
T82	0	5	0	0
T83	0	2	0	0
T84	0	12	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891312	12692	0	0
T2	238332	98	0	0
T3	24336	8	0	0
T4	58725	70	0	0
T5	58638	64	0	0
T6	6009	2	0	0
T7	4928	3	0	0
T8	12473	4	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	4	0	0
T12	0	31	0	0
T13	0	64	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25891312	975	0	0
T2	238332	6	0	0
T3	24336	8	0	0
T4	58725	0	0	0
T5	58638	0	0	0
T6	6009	0	0	0
T7	4928	0	0	0
T8	12473	4	0	0
T9	3433	0	0	0
T10	3678	0	0	0
T11	8090	0	0	0
T26	0	10	0	0
T42	0	13	0	0
T46	0	9	0	0
T81	0	10	0	0
T82	0	5	0	0
T83	0	2	0	0
T84	0	12	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	21878	0	0
T1	732	2	0	0
T2	15045	177	0	0
T3	1520	11	0	0
T4	3683	76	0	0
T5	3679	76	0	0
T6	374	6	0	0
T7	306	5	0	0
T8	777	7	0	0
T9	214	1	0	0
T10	230	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	1024	0	0
T2	15045	5	0	0
T3	1520	10	0	0
T4	3683	0	0	0
T5	3679	0	0	0
T6	374	0	0	0
T7	306	0	0	0
T8	777	6	0	0
T9	214	0	0	0
T10	230	0	0	0
T11	504	0	0	0
T26	0	10	0	0
T42	0	9	0	0
T46	0	9	0	0
T47	0	1	0	0
T81	0	9	0	0
T82	0	8	0	0
T83	0	2	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	21878	0	0
T1	732	2	0	0
T2	15045	177	0	0
T3	1520	11	0	0
T4	3683	76	0	0
T5	3679	76	0	0
T6	374	6	0	0
T7	306	5	0	0
T8	777	7	0	0
T9	214	1	0	0
T10	230	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1635037	1024	0	0
T2	15045	5	0	0
T3	1520	10	0	0
T4	3683	0	0	0
T5	3679	0	0	0
T6	374	0	0	0
T7	306	0	0	0
T8	777	6	0	0
T9	214	0	0	0
T10	230	0	0	0
T11	504	0	0	0
T26	0	10	0	0
T42	0	9	0	0
T46	0	9	0	0
T47	0	1	0	0
T81	0	9	0	0
T82	0	8	0	0
T83	0	2	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	14157	0	0
T2	119167	115	0	0
T3	12167	9	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	6	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	1063	0	0
T2	119167	6	0	0
T3	12167	9	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	6	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T26	0	12	0	0
T42	0	10	0	0
T46	0	11	0	0
T81	0	13	0	0
T82	0	7	0	0
T83	0	4	0	0
T85	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	14157	0	0
T2	119167	115	0	0
T3	12167	9	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	6	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	1063	0	0
T2	119167	6	0	0
T3	12167	9	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	6	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T26	0	12	0	0
T42	0	10	0	0
T46	0	11	0	0
T81	0	13	0	0
T82	0	7	0	0
T83	0	4	0	0
T85	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	14217	0	0
T2	119167	115	0	0
T3	12167	11	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	8	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	1137	0	0
T2	119167	6	0	0
T3	12167	11	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	8	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T26	0	13	0	0
T42	0	13	0	0
T46	0	9	0	0
T81	0	12	0	0
T82	0	10	0	0
T83	0	3	0	0
T84	0	13	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	14217	0	0
T2	119167	115	0	0
T3	12167	11	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	8	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	1137	0	0
T2	119167	6	0	0
T3	12167	11	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	8	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T26	0	13	0	0
T42	0	13	0	0
T46	0	9	0	0
T81	0	12	0	0
T82	0	10	0	0
T83	0	3	0	0
T84	0	13	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	14274	0	0
T2	119167	115	0	0
T3	12167	13	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	9	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	1188	0	0
T2	119167	6	0	0
T3	12167	13	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	9	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T26	0	14	0	0
T42	0	12	0	0
T46	0	10	0	0
T81	0	15	0	0
T82	0	11	0	0
T83	0	5	0	0
T84	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	14274	0	0
T2	119167	115	0	0
T3	12167	13	0	0
T4	29357	75	0	0
T5	29323	75	0	0
T6	3005	4	0	0
T7	2463	4	0	0
T8	6234	9	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	4	0	0
T12	0	34	0	0
T13	0	75	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12945437	1188	0	0
T2	119167	6	0	0
T3	12167	13	0	0
T4	29357	0	0	0
T5	29323	0	0	0
T6	3005	0	0	0
T7	2463	0	0	0
T8	6234	9	0	0
T9	1717	0	0	0
T10	1837	0	0	0
T11	4043	0	0	0
T26	0	14	0	0
T42	0	12	0	0
T46	0	10	0	0
T81	0	15	0	0
T82	0	11	0	0
T83	0	5	0	0
T84	0	10	0	0