Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12197588	8457	0	0
alert_regwen_rd_A	12197588	3683	0	0
cpu_regwen_rd_A	12197588	3975	0	0
sw_rst_ctrl_n_0_rd_A	12197588	8520	0	0
sw_rst_ctrl_n_1_rd_A	12197588	8546	0	0
sw_rst_ctrl_n_2_rd_A	12197588	8540	0	0
sw_rst_ctrl_n_3_rd_A	12197588	8685	0	0
sw_rst_ctrl_n_4_rd_A	12197588	8720	0	0
sw_rst_ctrl_n_5_rd_A	12197588	8634	0	0
sw_rst_ctrl_n_6_rd_A	12197588	8507	0	0
sw_rst_ctrl_n_7_rd_A	12197588	8914	0	0
sw_rst_regwen_0_rd_A	12197588	4378	0	0
sw_rst_regwen_1_rd_A	12197588	4303	0	0
sw_rst_regwen_2_rd_A	12197588	4263	0	0
sw_rst_regwen_3_rd_A	12197588	4309	0	0
sw_rst_regwen_4_rd_A	12197588	4194	0	0
sw_rst_regwen_5_rd_A	12197588	4285	0	0
sw_rst_regwen_6_rd_A	12197588	4278	0	0
sw_rst_regwen_7_rd_A	12197588	4313	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8457	0	0
T58	2076	8	0	0
T60	2925	336	0	0
T61	6872	131	0	0
T62	2831	163	0	0
T63	18787	5	0	0
T64	9724	378	0	0
T68	2551	11	0	0
T71	8893	1	0	0
T72	9310	1	0	0
T73	8173	252	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	3683	0	0
T84	133735	88	0	0
T90	14146	0	0	0
T91	0	159	0	0
T93	0	67	0	0
T99	0	106	0	0
T100	0	35	0	0
T111	0	153	0	0
T112	0	65	0	0
T113	0	54	0	0
T114	0	323	0	0
T115	0	57	0	0
T116	5546	0	0	0
T117	4447	0	0	0
T118	2259	0	0	0
T119	1742	0	0	0
T120	5646	0	0	0
T121	2451	0	0	0
T122	1340	0	0	0
T123	3352	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	3975	0	0
T84	133735	101	0	0
T90	14146	0	0	0
T91	0	152	0	0
T93	0	77	0	0
T99	0	94	0	0
T100	0	21	0	0
T111	0	153	0	0
T112	0	81	0	0
T113	0	30	0	0
T114	0	362	0	0
T115	0	32	0	0
T116	5546	0	0	0
T117	4447	0	0	0
T118	2259	0	0	0
T119	1742	0	0	0
T120	5646	0	0	0
T121	2451	0	0	0
T122	1340	0	0	0
T123	3352	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8520	0	0
T3	12077	196	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	9	0	0
T28	0	7	0	0
T53	369586	0	0	0
T84	0	150	0	0
T91	0	144	0	0
T116	0	69	0	0
T124	0	49	0	0
T125	0	8	0	0
T126	0	6	0	0
T127	0	173	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8546	0	0
T3	12077	177	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	18	0	0
T28	0	12	0	0
T53	369586	0	0	0
T84	0	180	0	0
T91	0	168	0	0
T116	0	59	0	0
T124	0	56	0	0
T125	0	8	0	0
T126	0	14	0	0
T127	0	210	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8540	0	0
T3	12077	174	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	14	0	0
T28	0	11	0	0
T53	369586	0	0	0
T84	0	200	0	0
T91	0	134	0	0
T116	0	54	0	0
T124	0	64	0	0
T125	0	4	0	0
T126	0	17	0	0
T127	0	230	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8685	0	0
T3	12077	161	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	19	0	0
T28	0	10	0	0
T53	369586	0	0	0
T84	0	174	0	0
T91	0	203	0	0
T116	0	66	0	0
T124	0	73	0	0
T125	0	6	0	0
T126	0	13	0	0
T127	0	197	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8720	0	0
T3	12077	184	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	9	0	0
T28	0	14	0	0
T53	369586	0	0	0
T84	0	164	0	0
T91	0	190	0	0
T116	0	63	0	0
T124	0	62	0	0
T125	0	20	0	0
T126	0	7	0	0
T127	0	193	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8634	0	0
T3	12077	218	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	6	0	0
T28	0	5	0	0
T53	369586	0	0	0
T84	0	189	0	0
T91	0	145	0	0
T116	0	63	0	0
T124	0	79	0	0
T125	0	16	0	0
T126	0	12	0	0
T127	0	179	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8507	0	0
T3	12077	173	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	16	0	0
T28	0	6	0	0
T53	369586	0	0	0
T84	0	165	0	0
T91	0	156	0	0
T116	0	75	0	0
T124	0	64	0	0
T125	0	8	0	0
T126	0	10	0	0
T127	0	203	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	8914	0	0
T3	12077	208	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	15	0	0
T28	0	8	0	0
T53	369586	0	0	0
T84	0	202	0	0
T91	0	218	0	0
T116	0	52	0	0
T124	0	82	0	0
T125	0	11	0	0
T126	0	16	0	0
T127	0	201	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4378	0	0
T3	12077	38	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	3	0	0
T53	369586	0	0	0
T84	0	93	0	0
T91	0	189	0	0
T93	0	39	0	0
T99	0	93	0	0
T100	0	41	0	0
T127	0	32	0	0
T128	0	12	0	0
T129	0	22	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4303	0	0
T3	12077	23	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	3	0	0
T53	369586	0	0	0
T84	0	67	0	0
T91	0	199	0	0
T93	0	44	0	0
T99	0	119	0	0
T100	0	8	0	0
T127	0	23	0	0
T128	0	12	0	0
T129	0	14	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4263	0	0
T3	12077	26	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	7	0	0
T53	369586	0	0	0
T84	0	72	0	0
T91	0	138	0	0
T93	0	66	0	0
T99	0	97	0	0
T100	0	36	0	0
T127	0	30	0	0
T128	0	8	0	0
T129	0	32	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4309	0	0
T3	12077	33	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	11	0	0
T53	369586	0	0	0
T84	0	103	0	0
T91	0	191	0	0
T93	0	71	0	0
T99	0	97	0	0
T100	0	27	0	0
T127	0	33	0	0
T128	0	8	0	0
T129	0	26	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4194	0	0
T3	12077	33	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T53	369586	0	0	0
T84	0	80	0	0
T91	0	124	0	0
T93	0	31	0	0
T99	0	92	0	0
T100	0	27	0	0
T127	0	11	0	0
T128	0	4	0	0
T129	0	31	0	0
T130	0	17	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4285	0	0
T3	12077	26	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T53	369586	0	0	0
T84	0	78	0	0
T91	0	175	0	0
T93	0	44	0	0
T99	0	104	0	0
T100	0	32	0	0
T127	0	34	0	0
T128	0	9	0	0
T129	0	26	0	0
T130	0	28	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4278	0	0
T3	12077	21	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	7	0	0
T53	369586	0	0	0
T84	0	105	0	0
T91	0	164	0	0
T93	0	51	0	0
T99	0	88	0	0
T100	0	39	0	0
T127	0	45	0	0
T128	0	2	0	0
T129	0	36	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12197588	4313	0	0
T3	12077	30	0	0
T4	26059	0	0	0
T5	26366	0	0	0
T6	2810	0	0	0
T7	2270	0	0	0
T8	6169	0	0	0
T9	1674	0	0	0
T10	1820	0	0	0
T11	3758	0	0	0
T14	0	13	0	0
T53	369586	0	0	0
T84	0	79	0	0
T91	0	139	0	0
T93	0	40	0	0
T99	0	103	0	0
T100	0	30	0	0
T127	0	38	0	0
T128	0	11	0	0
T129	0	27	0	0