Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 620648 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 375457 1 T1 2 T2 275 T3 1151



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 532050 1 T2 379 T3 1500 T4 99
values[0x0] 232159 1 T1 8 T2 158 T3 872
values[0x1] 231896 1 T1 7 T2 175 T3 828



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 520813 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 475292 1 T1 4 T2 348 T3 1471



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3491 1 T2 2 T3 15 T5 15
valid_sources[0x01] 2922 1 T2 1 T3 9 T5 7
valid_sources[0x02] 3314 1 T1 1 T2 4 T3 13
valid_sources[0x03] 3803 1 T2 5 T3 15 T5 9
valid_sources[0x04] 3356 1 T2 3 T3 11 T5 17
valid_sources[0x05] 3959 1 T2 2 T3 17 T5 16
valid_sources[0x06] 3652 1 T2 1 T3 6 T5 14
valid_sources[0x07] 3931 1 T2 5 T3 9 T5 18
valid_sources[0x08] 4001 1 T2 3 T3 19 T5 13
valid_sources[0x09] 3178 1 T2 2 T3 11 T5 8
valid_sources[0x0a] 3539 1 T2 5 T3 9 T5 14
valid_sources[0x0b] 3738 1 T2 3 T3 16 T5 12
valid_sources[0x0c] 3658 1 T3 26 T5 11 T8 4
valid_sources[0x0d] 3468 1 T2 1 T3 4 T5 16
valid_sources[0x0e] 3645 1 T2 1 T3 17 T5 14
valid_sources[0x0f] 2959 1 T2 5 T3 15 T5 10
valid_sources[0x10] 3908 1 T2 6 T3 14 T5 14
valid_sources[0x11] 3173 1 T2 6 T3 24 T5 12
valid_sources[0x12] 3252 1 T3 19 T5 8 T8 16
valid_sources[0x13] 3784 1 T2 2 T3 12 T5 24
valid_sources[0x14] 3600 1 T2 2 T3 9 T5 12
valid_sources[0x15] 3542 1 T3 15 T5 3 T8 15
valid_sources[0x16] 3079 1 T2 1 T3 21 T5 18
valid_sources[0x17] 3217 1 T2 4 T3 16 T5 17
valid_sources[0x18] 3534 1 T2 7 T3 5 T5 12
valid_sources[0x19] 3784 1 T2 2 T3 8 T5 10
valid_sources[0x1a] 4549 1 T3 17 T5 7 T8 24
valid_sources[0x1b] 3364 1 T2 4 T3 17 T5 8
valid_sources[0x1c] 3623 1 T2 3 T3 5 T5 9
valid_sources[0x1d] 4302 1 T3 13 T5 15 T8 12
valid_sources[0x1e] 3264 1 T3 5 T5 7 T8 15
valid_sources[0x1f] 3632 1 T2 1 T3 2 T5 14
valid_sources[0x20] 3252 1 T3 13 T5 16 T8 15
valid_sources[0x21] 3633 1 T3 11 T5 10 T8 11
valid_sources[0x22] 3559 1 T2 2 T3 14 T5 8
valid_sources[0x23] 3201 1 T2 10 T3 11 T5 18
valid_sources[0x24] 4818 1 T2 3 T3 8 T5 12
valid_sources[0x25] 4735 1 T2 4 T3 26 T5 12
valid_sources[0x26] 3906 1 T2 2 T3 20 T5 15
valid_sources[0x27] 3273 1 T2 4 T3 15 T5 15
valid_sources[0x28] 3603 1 T3 13 T5 15 T8 13
valid_sources[0x29] 5058 1 T2 1 T3 7 T5 20
valid_sources[0x2a] 3152 1 T3 15 T5 8 T8 12
valid_sources[0x2b] 4756 1 T2 3 T3 22 T5 26
valid_sources[0x2c] 4580 1 T2 1 T3 16 T5 33
valid_sources[0x2d] 3023 1 T2 3 T3 9 T5 15
valid_sources[0x2e] 4698 1 T2 4 T3 9 T5 13
valid_sources[0x2f] 4666 1 T2 2 T3 10 T5 18
valid_sources[0x30] 3362 1 T3 17 T5 10 T8 8
valid_sources[0x31] 3207 1 T2 5 T3 16 T5 8
valid_sources[0x32] 3247 1 T2 3 T3 11 T5 12
valid_sources[0x33] 3470 1 T2 1 T3 5 T5 12
valid_sources[0x34] 3042 1 T3 8 T5 11 T8 8
valid_sources[0x35] 3378 1 T2 1 T3 14 T5 16
valid_sources[0x36] 3699 1 T2 3 T3 4 T5 18
valid_sources[0x37] 4355 1 T3 10 T5 6 T8 12
valid_sources[0x38] 4676 1 T3 13 T5 13 T8 10
valid_sources[0x39] 3078 1 T3 5 T5 15 T7 1
valid_sources[0x3a] 3646 1 T2 3 T3 9 T5 10
valid_sources[0x3b] 4413 1 T2 5 T3 16 T5 14
valid_sources[0x3c] 3167 1 T2 3 T3 20 T5 18
valid_sources[0x3d] 4518 1 T2 3 T3 13 T5 7
valid_sources[0x3e] 4603 1 T2 3 T3 12 T5 11
valid_sources[0x3f] 6354 1 T2 6 T3 22 T5 9
valid_sources[0x40] 3264 1 T2 1 T3 9 T5 11
valid_sources[0x41] 3384 1 T2 4 T3 10 T5 9
valid_sources[0x42] 3619 1 T2 5 T3 6 T5 18
valid_sources[0x43] 6679 1 T2 3 T3 22 T5 8
valid_sources[0x44] 3739 1 T3 12 T5 15 T8 21
valid_sources[0x45] 3385 1 T2 3 T3 16 T5 16
valid_sources[0x46] 7054 1 T1 2 T2 5 T3 15
valid_sources[0x47] 3864 1 T2 5 T3 12 T5 21
valid_sources[0x48] 4641 1 T3 17 T5 10 T8 9
valid_sources[0x49] 3355 1 T2 1 T3 12 T5 18
valid_sources[0x4a] 3837 1 T2 1 T3 19 T5 18
valid_sources[0x4b] 3313 1 T3 19 T5 17 T8 11
valid_sources[0x4c] 3814 1 T2 1 T3 23 T5 13
valid_sources[0x4d] 3354 1 T2 2 T3 14 T5 8
valid_sources[0x4e] 3020 1 T2 1 T3 11 T5 8
valid_sources[0x4f] 3684 1 T2 1 T3 21 T5 12
valid_sources[0x50] 4115 1 T2 2 T3 21 T5 6
valid_sources[0x51] 5585 1 T2 1 T3 7 T5 12
valid_sources[0x52] 3557 1 T3 20 T5 14 T8 15
valid_sources[0x53] 4413 1 T2 4 T3 7 T5 8
valid_sources[0x54] 4758 1 T2 2 T3 17 T5 15
valid_sources[0x55] 3124 1 T1 3 T2 2 T3 17
valid_sources[0x56] 5227 1 T1 1 T2 1 T3 14
valid_sources[0x57] 3109 1 T2 9 T3 17 T5 17
valid_sources[0x58] 3257 1 T2 5 T3 11 T5 13
valid_sources[0x59] 3485 1 T1 1 T2 2 T3 8
valid_sources[0x5a] 3386 1 T3 16 T5 14 T8 10
valid_sources[0x5b] 3073 1 T2 6 T3 11 T5 14
valid_sources[0x5c] 4701 1 T2 2 T3 11 T5 18
valid_sources[0x5d] 3458 1 T2 6 T3 13 T5 20
valid_sources[0x5e] 6572 1 T2 3 T3 14 T5 7
valid_sources[0x5f] 3650 1 T2 10 T3 10 T5 11
valid_sources[0x60] 3636 1 T2 7 T3 13 T5 9
valid_sources[0x61] 3248 1 T2 1 T3 14 T5 8
valid_sources[0x62] 4032 1 T2 8 T3 7 T5 11
valid_sources[0x63] 2952 1 T3 9 T5 10 T8 15
valid_sources[0x64] 3277 1 T2 1 T3 18 T5 11
valid_sources[0x65] 3848 1 T2 1 T3 12 T5 21
valid_sources[0x66] 3455 1 T2 2 T3 12 T5 8
valid_sources[0x67] 3899 1 T2 1 T3 13 T5 16
valid_sources[0x68] 3276 1 T2 1 T3 7 T5 17
valid_sources[0x69] 3110 1 T2 3 T3 13 T5 13
valid_sources[0x6a] 4212 1 T2 5 T3 8 T5 15
valid_sources[0x6b] 3337 1 T2 3 T3 18 T5 18
valid_sources[0x6c] 3443 1 T3 13 T5 7 T8 7
valid_sources[0x6d] 3135 1 T2 10 T3 18 T5 8
valid_sources[0x6e] 5949 1 T2 2 T3 9 T5 6
valid_sources[0x6f] 3100 1 T2 4 T3 13 T5 16
valid_sources[0x70] 4248 1 T2 2 T3 13 T5 7
valid_sources[0x71] 6804 1 T3 8 T5 4 T8 5
valid_sources[0x72] 4400 1 T2 9 T3 15 T5 8
valid_sources[0x73] 3802 1 T2 3 T3 5 T5 12
valid_sources[0x74] 3430 1 T2 4 T3 16 T5 21
valid_sources[0x75] 3147 1 T2 1 T3 14 T5 12
valid_sources[0x76] 3246 1 T2 6 T3 6 T5 8
valid_sources[0x77] 6738 1 T3 9 T5 10 T8 13
valid_sources[0x78] 3546 1 T2 2 T3 17 T5 22
valid_sources[0x79] 2968 1 T2 2 T3 10 T5 8
valid_sources[0x7a] 4741 1 T2 4 T3 12 T5 7
valid_sources[0x7b] 6855 1 T2 3 T3 5 T5 9
valid_sources[0x7c] 4561 1 T2 1 T3 21 T5 15
valid_sources[0x7d] 3874 1 T2 2 T3 11 T5 21
valid_sources[0x7e] 3993 1 T2 4 T3 26 T5 12
valid_sources[0x7f] 3412 1 T2 2 T3 15 T5 3
valid_sources[0x80] 4852 1 T2 2 T3 13 T5 7



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 250214 1 T2 185 T3 687 T4 44
values[0x0] all_enables biggest_size 81554 1 T1 1 T2 56 T3 309
values[0x1] all_enables biggest_size 43689 1 T1 1 T2 34 T3 155

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%