Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T11
0	1	Covered	T4,T9,T11
1	0	Covered	T9,T11,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T4,T9,T11
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56891121	9000	0	0
CascadeEffAonToRstPorAboveRise_A	56891121	9000	0	0
CascadeEffAonToRstPorIoAboveFall_A	54613247	9000	0	0
CascadeEffAonToRstPorIoAboveRise_A	54613247	9000	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27307654	9000	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27307654	9000	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13653613	9000	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13653613	9000	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27307574	9000	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27307574	9000	0	0
CascadeLcToLcAboveFall_A	56891121	22133	0	0
CascadeLcToLcAboveRise_A	56891121	22133	0	0
CascadeLcToLcAonAboveFall_A	1723566	22133	0	0
CascadeLcToLcAonAboveRise_A	1723566	22133	0	0
CascadeLcToLcShadowedAboveFall_A	56891121	22133	0	0
CascadeLcToLcShadowedAboveRise_A	56891121	22133	0	0
CascadePorToAonAboveFall_A	1723566	7167	0	0
CascadeSysToSysAboveFall_A	56891121	22133	0	0
CascadeSysToSysAboveRise_A	56891121	22133	0	0
ScanRstToAonRise_A	1723566	241	0	0
StablePorToAonRise_A	1723566	9000	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12167666	22133	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12167666	22133	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12167666	22133	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12167666	22133	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13653613	22133	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13653613	22133	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12167666	22133	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12167666	22133	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12167666	22133	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12167666	22133	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	9000	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	27	0	0
T4	17064	2	0	0
T5	235849	27	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	27	0	0
T9	142029	28	0	0
T10	187567	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	9000	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	27	0	0
T4	17064	2	0	0
T5	235849	27	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	27	0	0
T9	142029	28	0	0
T10	187567	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54613247	9000	0	0
T1	6585	1	0	0
T2	32293	1	0	0
T3	117288	27	0	0
T4	16381	2	0	0
T5	226456	27	0	0
T6	16261	2	0	0
T7	9275	2	0	0
T8	117299	27	0	0
T9	136335	28	0	0
T10	180074	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54613247	9000	0	0
T1	6585	1	0	0
T2	32293	1	0	0
T3	117288	27	0	0
T4	16381	2	0	0
T5	226456	27	0	0
T6	16261	2	0	0
T7	9275	2	0	0
T8	117299	27	0	0
T9	136335	28	0	0
T10	180074	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307654	9000	0	0
T1	3292	1	0	0
T2	16146	1	0	0
T3	58643	27	0	0
T4	8186	2	0	0
T5	113238	27	0	0
T6	8130	2	0	0
T7	4637	2	0	0
T8	58667	27	0	0
T9	68158	28	0	0
T10	90028	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307654	9000	0	0
T1	3292	1	0	0
T2	16146	1	0	0
T3	58643	27	0	0
T4	8186	2	0	0
T5	113238	27	0	0
T6	8130	2	0	0
T7	4637	2	0	0
T8	58667	27	0	0
T9	68158	28	0	0
T10	90028	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	9000	0	0
T1	1644	1	0	0
T2	8073	1	0	0
T3	29321	27	0	0
T4	4094	2	0	0
T5	56616	27	0	0
T6	4064	2	0	0
T7	2318	2	0	0
T8	29334	27	0	0
T9	34084	28	0	0
T10	45013	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	9000	0	0
T1	1644	1	0	0
T2	8073	1	0	0
T3	29321	27	0	0
T4	4094	2	0	0
T5	56616	27	0	0
T6	4064	2	0	0
T7	2318	2	0	0
T8	29334	27	0	0
T9	34084	28	0	0
T10	45013	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307574	9000	0	0
T1	3292	1	0	0
T2	16147	1	0	0
T3	58647	27	0	0
T4	8189	2	0	0
T5	113242	27	0	0
T6	8130	2	0	0
T7	4636	2	0	0
T8	58658	27	0	0
T9	68172	28	0	0
T10	90047	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307574	9000	0	0
T1	3292	1	0	0
T2	16147	1	0	0
T3	58647	27	0	0
T4	8189	2	0	0
T5	113242	27	0	0
T6	8130	2	0	0
T7	4636	2	0	0
T8	58658	27	0	0
T9	68172	28	0	0
T10	90047	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	22133	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	102	0	0
T4	17064	6	0	0
T5	235849	102	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	102	0	0
T9	142029	79	0	0
T10	187567	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	22133	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	102	0	0
T4	17064	6	0	0
T5	235849	102	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	102	0	0
T9	142029	79	0	0
T10	187567	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	22133	0	0
T1	204	1	0	0
T2	1007	1	0	0
T3	3681	102	0	0
T4	511	6	0	0
T5	7092	102	0	0
T6	506	2	0	0
T7	288	2	0	0
T8	3681	102	0	0
T9	4308	79	0	0
T10	5641	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	22133	0	0
T1	204	1	0	0
T2	1007	1	0	0
T3	3681	102	0	0
T4	511	6	0	0
T5	7092	102	0	0
T6	506	2	0	0
T7	288	2	0	0
T8	3681	102	0	0
T9	4308	79	0	0
T10	5641	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	22133	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	102	0	0
T4	17064	6	0	0
T5	235849	102	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	102	0	0
T9	142029	79	0	0
T10	187567	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	22133	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	102	0	0
T4	17064	6	0	0
T5	235849	102	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	102	0	0
T9	142029	79	0	0
T10	187567	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	7167	0	0
T1	204	1	0	0
T2	1007	1	0	0
T3	3681	27	0	0
T4	511	1	0	0
T5	7092	27	0	0
T6	506	11	0	0
T7	288	3	0	0
T8	3681	27	0	0
T9	4308	13	0	0
T10	5641	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	22133	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	102	0	0
T4	17064	6	0	0
T5	235849	102	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	102	0	0
T9	142029	79	0	0
T10	187567	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56891121	22133	0	0
T1	6859	1	0	0
T2	33641	1	0	0
T3	122198	102	0	0
T4	17064	6	0	0
T5	235849	102	0	0
T6	16938	2	0	0
T7	9661	2	0	0
T8	122183	102	0	0
T9	142029	79	0	0
T10	187567	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	241	0	0
T9	4308	3	0	0
T10	5641	0	0	0
T11	11765	2	0	0
T12	173	0	0	0
T13	586	0	0	0
T14	731	0	0	0
T15	298	0	0	0
T16	404	0	0	0
T23	9184	1	0	0
T24	2676	1	0	0
T37	0	3	0	0
T38	0	7	0	0
T43	0	1	0	0
T74	0	4	0	0
T75	0	12	0	0
T87	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	9000	0	0
T1	204	1	0	0
T2	1007	1	0	0
T3	3681	27	0	0
T4	511	2	0	0
T5	7092	27	0	0
T6	506	2	0	0
T7	288	2	0	0
T8	3681	27	0	0
T9	4308	28	0	0
T10	5641	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	22133	0	0
T1	1644	1	0	0
T2	8073	1	0	0
T3	29321	102	0	0
T4	4094	6	0	0
T5	56616	102	0	0
T6	4064	2	0	0
T7	2318	2	0	0
T8	29334	102	0	0
T9	34084	79	0	0
T10	45013	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	22133	0	0
T1	1644	1	0	0
T2	8073	1	0	0
T3	29321	102	0	0
T4	4094	6	0	0
T5	56616	102	0	0
T6	4064	2	0	0
T7	2318	2	0	0
T8	29334	102	0	0
T9	34084	79	0	0
T10	45013	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12167666	22133	0	0
T1	1627	1	0	0
T2	8030	1	0	0
T3	26423	102	0	0
T4	3949	6	0	0
T5	53599	102	0	0
T6	3974	2	0	0
T7	2275	2	0	0
T8	26047	102	0	0
T9	28224	79	0	0
T10	41621	102	0	0