Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T11
1	0	Covered	T3,T4,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13653613	14055	0	0
gen_assertions[0].RstEnOn_A	13653613	1096	0	0
gen_assertions[0].RstNOff_A	13653613	14055	0	0
gen_assertions[0].RstNOn_A	13653613	1096	0	0
gen_assertions[1].RstEnOff_A	54613247	12817	0	0
gen_assertions[1].RstEnOn_A	54613247	1070	0	0
gen_assertions[1].RstNOff_A	54613247	12817	0	0
gen_assertions[1].RstNOn_A	54613247	1070	0	0
gen_assertions[2].RstEnOff_A	27307654	12867	0	0
gen_assertions[2].RstEnOn_A	27307654	1073	0	0
gen_assertions[2].RstNOff_A	27307654	12867	0	0
gen_assertions[2].RstNOn_A	27307654	1073	0	0
gen_assertions[3].RstEnOff_A	27307574	12900	0	0
gen_assertions[3].RstEnOn_A	27307574	1101	0	0
gen_assertions[3].RstNOff_A	27307574	12900	0	0
gen_assertions[3].RstNOn_A	27307574	1101	0	0
gen_assertions[4].RstEnOff_A	1723566	22005	0	0
gen_assertions[4].RstEnOn_A	1723566	1145	0	0
gen_assertions[4].RstNOff_A	1723566	22005	0	0
gen_assertions[4].RstNOn_A	1723566	1145	0	0
gen_assertions[5].RstEnOff_A	13653613	14314	0	0
gen_assertions[5].RstEnOn_A	13653613	1222	0	0
gen_assertions[5].RstNOff_A	13653613	14314	0	0
gen_assertions[5].RstNOn_A	13653613	1222	0	0
gen_assertions[6].RstEnOff_A	13653613	14326	0	0
gen_assertions[6].RstEnOn_A	13653613	1226	0	0
gen_assertions[6].RstNOff_A	13653613	14326	0	0
gen_assertions[6].RstNOn_A	13653613	1226	0	0
gen_assertions[7].RstEnOff_A	13653613	14368	0	0
gen_assertions[7].RstEnOn_A	13653613	1271	0	0
gen_assertions[7].RstNOff_A	13653613	14368	0	0
gen_assertions[7].RstNOn_A	13653613	1271	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14055	0	0
T2	8073	1	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	54	0	0
T10	45013	75	0	0
T11	0	74	0	0
T12	1404	0	0	0
T13	0	5	0	0
T23	0	67	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1096	0	0
T2	8073	1	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	3	0	0
T10	45013	0	0	0
T11	0	4	0	0
T12	1404	0	0	0
T13	0	1	0	0
T23	0	16	0	0
T38	0	10	0	0
T43	0	1	0	0
T50	0	1	0	0
T72	0	4	0	0
T73	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14055	0	0
T2	8073	1	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	54	0	0
T10	45013	75	0	0
T11	0	74	0	0
T12	1404	0	0	0
T13	0	5	0	0
T23	0	67	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1096	0	0
T2	8073	1	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	3	0	0
T10	45013	0	0	0
T11	0	4	0	0
T12	1404	0	0	0
T13	0	1	0	0
T23	0	16	0	0
T38	0	10	0	0
T43	0	1	0	0
T50	0	1	0	0
T72	0	4	0	0
T73	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54613247	12817	0	0
T2	32293	3	0	0
T3	117288	68	0	0
T4	16381	3	0	0
T5	226456	67	0	0
T6	16261	0	0	0
T7	9275	0	0	0
T8	117299	66	0	0
T9	136335	49	0	0
T10	180074	71	0	0
T11	0	63	0	0
T12	5620	0	0	0
T13	0	4	0	0
T23	0	57	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54613247	1070	0	0
T2	32293	3	0	0
T3	117288	0	0	0
T4	16381	0	0	0
T5	226456	0	0	0
T6	16261	0	0	0
T7	9275	0	0	0
T8	117299	0	0	0
T9	136335	6	0	0
T10	180074	0	0	0
T11	0	4	0	0
T12	5620	0	0	0
T23	0	13	0	0
T38	0	11	0	0
T44	0	5	0	0
T45	0	4	0	0
T74	0	21	0	0
T75	0	19	0	0
T76	0	9	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54613247	12817	0	0
T2	32293	3	0	0
T3	117288	68	0	0
T4	16381	3	0	0
T5	226456	67	0	0
T6	16261	0	0	0
T7	9275	0	0	0
T8	117299	66	0	0
T9	136335	49	0	0
T10	180074	71	0	0
T11	0	63	0	0
T12	5620	0	0	0
T13	0	4	0	0
T23	0	57	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54613247	1070	0	0
T2	32293	3	0	0
T3	117288	0	0	0
T4	16381	0	0	0
T5	226456	0	0	0
T6	16261	0	0	0
T7	9275	0	0	0
T8	117299	0	0	0
T9	136335	6	0	0
T10	180074	0	0	0
T11	0	4	0	0
T12	5620	0	0	0
T23	0	13	0	0
T38	0	11	0	0
T44	0	5	0	0
T45	0	4	0	0
T74	0	21	0	0
T75	0	19	0	0
T76	0	9	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307654	12867	0	0
T2	16146	4	0	0
T3	58643	68	0	0
T4	8186	3	0	0
T5	113238	67	0	0
T6	8130	0	0	0
T7	4637	0	0	0
T8	58667	66	0	0
T9	68158	49	0	0
T10	90028	71	0	0
T11	0	63	0	0
T12	2809	0	0	0
T13	0	4	0	0
T23	0	61	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307654	1073	0	0
T2	16146	4	0	0
T3	58643	0	0	0
T4	8186	0	0	0
T5	113238	0	0	0
T6	8130	0	0	0
T7	4637	0	0	0
T8	58667	0	0	0
T9	68158	6	0	0
T10	90028	0	0	0
T11	0	4	0	0
T12	2809	0	0	0
T23	0	16	0	0
T38	0	8	0	0
T44	0	6	0	0
T45	0	2	0	0
T74	0	20	0	0
T75	0	19	0	0
T76	0	9	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307654	12867	0	0
T2	16146	4	0	0
T3	58643	68	0	0
T4	8186	3	0	0
T5	113238	67	0	0
T6	8130	0	0	0
T7	4637	0	0	0
T8	58667	66	0	0
T9	68158	49	0	0
T10	90028	71	0	0
T11	0	63	0	0
T12	2809	0	0	0
T13	0	4	0	0
T23	0	61	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307654	1073	0	0
T2	16146	4	0	0
T3	58643	0	0	0
T4	8186	0	0	0
T5	113238	0	0	0
T6	8130	0	0	0
T7	4637	0	0	0
T8	58667	0	0	0
T9	68158	6	0	0
T10	90028	0	0	0
T11	0	4	0	0
T12	2809	0	0	0
T23	0	16	0	0
T38	0	8	0	0
T44	0	6	0	0
T45	0	2	0	0
T74	0	20	0	0
T75	0	19	0	0
T76	0	9	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307574	12900	0	0
T2	16147	4	0	0
T3	58647	68	0	0
T4	8189	3	0	0
T5	113242	67	0	0
T6	8130	0	0	0
T7	4636	0	0	0
T8	58658	66	0	0
T9	68172	49	0	0
T10	90047	71	0	0
T11	0	61	0	0
T12	2809	0	0	0
T13	0	4	0	0
T23	0	53	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307574	1101	0	0
T2	16147	4	0	0
T3	58647	0	0	0
T4	8189	0	0	0
T5	113242	0	0	0
T6	8130	0	0	0
T7	4636	0	0	0
T8	58658	0	0	0
T9	68172	6	0	0
T10	90047	0	0	0
T11	0	2	0	0
T12	2809	0	0	0
T23	0	8	0	0
T38	0	13	0	0
T43	0	1	0	0
T44	0	10	0	0
T45	0	5	0	0
T74	0	24	0	0
T75	0	16	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307574	12900	0	0
T2	16147	4	0	0
T3	58647	68	0	0
T4	8189	3	0	0
T5	113242	67	0	0
T6	8130	0	0	0
T7	4636	0	0	0
T8	58658	66	0	0
T9	68172	49	0	0
T10	90047	71	0	0
T11	0	61	0	0
T12	2809	0	0	0
T13	0	4	0	0
T23	0	53	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27307574	1101	0	0
T2	16147	4	0	0
T3	58647	0	0	0
T4	8189	0	0	0
T5	113242	0	0	0
T6	8130	0	0	0
T7	4636	0	0	0
T8	58658	0	0	0
T9	68172	6	0	0
T10	90047	0	0	0
T11	0	2	0	0
T12	2809	0	0	0
T23	0	8	0	0
T38	0	13	0	0
T43	0	1	0	0
T44	0	10	0	0
T45	0	5	0	0
T74	0	24	0	0
T75	0	16	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	22005	0	0
T1	204	1	0	0
T2	1007	6	0	0
T3	3681	76	0	0
T4	511	6	0	0
T5	7092	97	0	0
T6	506	2	0	0
T7	288	2	0	0
T8	3681	75	0	0
T9	4308	80	0	0
T10	5641	89	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	1145	0	0
T2	1007	5	0	0
T3	3681	0	0	0
T4	511	0	0	0
T5	7092	0	0	0
T6	506	0	0	0
T7	288	0	0	0
T8	3681	0	0	0
T9	4308	6	0	0
T10	5641	0	0	0
T11	0	3	0	0
T12	173	0	0	0
T13	0	1	0	0
T23	0	17	0	0
T38	0	13	0	0
T44	0	9	0	0
T45	0	7	0	0
T74	0	25	0	0
T75	0	15	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	22005	0	0
T1	204	1	0	0
T2	1007	6	0	0
T3	3681	76	0	0
T4	511	6	0	0
T5	7092	97	0	0
T6	506	2	0	0
T7	288	2	0	0
T8	3681	75	0	0
T9	4308	80	0	0
T10	5641	89	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723566	1145	0	0
T2	1007	5	0	0
T3	3681	0	0	0
T4	511	0	0	0
T5	7092	0	0	0
T6	506	0	0	0
T7	288	0	0	0
T8	3681	0	0	0
T9	4308	6	0	0
T10	5641	0	0	0
T11	0	3	0	0
T12	173	0	0	0
T13	0	1	0	0
T23	0	17	0	0
T38	0	13	0	0
T44	0	9	0	0
T45	0	7	0	0
T74	0	25	0	0
T75	0	15	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14314	0	0
T2	8073	6	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	56	0	0
T10	45013	75	0	0
T11	0	74	0	0
T12	1404	0	0	0
T13	0	4	0	0
T23	0	64	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1222	0	0
T2	8073	6	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	6	0	0
T10	45013	0	0	0
T11	0	4	0	0
T12	1404	0	0	0
T23	0	13	0	0
T38	0	13	0	0
T44	0	7	0	0
T45	0	8	0	0
T50	0	1	0	0
T74	0	24	0	0
T75	0	16	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14314	0	0
T2	8073	6	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	56	0	0
T10	45013	75	0	0
T11	0	74	0	0
T12	1404	0	0	0
T13	0	4	0	0
T23	0	64	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1222	0	0
T2	8073	6	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	6	0	0
T10	45013	0	0	0
T11	0	4	0	0
T12	1404	0	0	0
T23	0	13	0	0
T38	0	13	0	0
T44	0	7	0	0
T45	0	8	0	0
T50	0	1	0	0
T74	0	24	0	0
T75	0	16	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14326	0	0
T2	8073	7	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	57	0	0
T10	45013	75	0	0
T11	0	73	0	0
T12	1404	0	0	0
T13	0	4	0	0
T23	0	61	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1226	0	0
T2	8073	7	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	6	0	0
T10	45013	0	0	0
T11	0	3	0	0
T12	1404	0	0	0
T23	0	9	0	0
T38	0	14	0	0
T44	0	13	0	0
T45	0	10	0	0
T50	0	1	0	0
T74	0	23	0	0
T75	0	13	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14326	0	0
T2	8073	7	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	57	0	0
T10	45013	75	0	0
T11	0	73	0	0
T12	1404	0	0	0
T13	0	4	0	0
T23	0	61	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1226	0	0
T2	8073	7	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	6	0	0
T10	45013	0	0	0
T11	0	3	0	0
T12	1404	0	0	0
T23	0	9	0	0
T38	0	14	0	0
T44	0	13	0	0
T45	0	10	0	0
T50	0	1	0	0
T74	0	23	0	0
T75	0	13	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14368	0	0
T2	8073	7	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	55	0	0
T10	45013	75	0	0
T11	0	74	0	0
T12	1404	0	0	0
T13	0	5	0	0
T23	0	63	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1271	0	0
T2	8073	7	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	4	0	0
T10	45013	0	0	0
T11	0	4	0	0
T12	1404	0	0	0
T13	0	1	0	0
T23	0	13	0	0
T38	0	10	0	0
T43	0	1	0	0
T44	0	11	0	0
T50	0	1	0	0
T74	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	14368	0	0
T2	8073	7	0	0
T3	29321	75	0	0
T4	4094	4	0	0
T5	56616	75	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	75	0	0
T9	34084	55	0	0
T10	45013	75	0	0
T11	0	74	0	0
T12	1404	0	0	0
T13	0	5	0	0
T23	0	63	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13653613	1271	0	0
T2	8073	7	0	0
T3	29321	0	0	0
T4	4094	0	0	0
T5	56616	0	0	0
T6	4064	0	0	0
T7	2318	0	0	0
T8	29334	0	0	0
T9	34084	4	0	0
T10	45013	0	0	0
T11	0	4	0	0
T12	1404	0	0	0
T13	0	1	0	0
T23	0	13	0	0
T38	0	10	0	0
T43	0	1	0	0
T44	0	11	0	0
T50	0	1	0	0
T74	0	13	0	0