Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12944564	7607	0	0
alert_regwen_rd_A	12944564	6509	0	0
cpu_regwen_rd_A	12944564	6478	0	0
sw_rst_ctrl_n_0_rd_A	12944564	12730	0	0
sw_rst_ctrl_n_1_rd_A	12944564	12818	0	0
sw_rst_ctrl_n_2_rd_A	12944564	12547	0	0
sw_rst_ctrl_n_3_rd_A	12944564	12473	0	0
sw_rst_ctrl_n_4_rd_A	12944564	12803	0	0
sw_rst_ctrl_n_5_rd_A	12944564	12479	0	0
sw_rst_ctrl_n_6_rd_A	12944564	12870	0	0
sw_rst_ctrl_n_7_rd_A	12944564	12809	0	0
sw_rst_regwen_0_rd_A	12944564	6975	0	0
sw_rst_regwen_1_rd_A	12944564	7106	0	0
sw_rst_regwen_2_rd_A	12944564	6897	0	0
sw_rst_regwen_3_rd_A	12944564	6878	0	0
sw_rst_regwen_4_rd_A	12944564	6692	0	0
sw_rst_regwen_5_rd_A	12944564	6878	0	0
sw_rst_regwen_6_rd_A	12944564	6722	0	0
sw_rst_regwen_7_rd_A	12944564	6759	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	7607	0	0
T49	20111	3	0	0
T51	11479	419	0	0
T52	13684	403	0	0
T53	4546	551	0	0
T58	2756	35	0	0
T59	19715	1	0	0
T78	3255	91	0	0
T79	25833	2	0	0
T80	4412	16	0	0
T81	7228	287	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6509	0	0
T17	4866	0	0	0
T23	67910	84	0	0
T24	16183	0	0	0
T37	17054	0	0	0
T38	91997	0	0	0
T39	5300	0	0	0
T43	5357	0	0	0
T57	1446	0	0	0
T70	4151	0	0	0
T72	4899	0	0	0
T74	0	150	0	0
T75	0	359	0	0
T84	0	24	0	0
T88	0	498	0	0
T89	0	90	0	0
T90	0	127	0	0
T92	0	309	0	0
T93	0	336	0	0
T106	0	99	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6478	0	0
T17	4866	0	0	0
T23	67910	67	0	0
T24	16183	0	0	0
T37	17054	0	0	0
T38	91997	0	0	0
T39	5300	0	0	0
T43	5357	0	0	0
T57	1446	0	0	0
T70	4151	0	0	0
T72	4899	0	0	0
T74	0	170	0	0
T75	0	306	0	0
T84	0	17	0	0
T88	0	447	0	0
T89	0	100	0	0
T90	0	63	0	0
T92	0	362	0	0
T93	0	338	0	0
T106	0	101	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12730	0	0
T2	8030	80	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	259	0	0
T43	0	2	0	0
T44	0	187	0	0
T50	0	17	0	0
T72	0	59	0	0
T73	0	33	0	0
T74	0	293	0	0
T75	0	402	0	0
T84	0	33	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12818	0	0
T2	8030	98	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	233	0	0
T44	0	166	0	0
T50	0	16	0	0
T72	0	70	0	0
T73	0	35	0	0
T74	0	305	0	0
T75	0	464	0	0
T84	0	34	0	0
T107	0	7	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12547	0	0
T2	8030	91	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	257	0	0
T43	0	14	0	0
T44	0	191	0	0
T50	0	16	0	0
T72	0	65	0	0
T73	0	17	0	0
T74	0	297	0	0
T75	0	424	0	0
T84	0	43	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12473	0	0
T2	8030	91	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	293	0	0
T43	0	7	0	0
T44	0	193	0	0
T50	0	10	0	0
T72	0	72	0	0
T73	0	16	0	0
T74	0	297	0	0
T75	0	455	0	0
T84	0	13	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12803	0	0
T2	8030	91	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	285	0	0
T43	0	3	0	0
T44	0	204	0	0
T50	0	11	0	0
T72	0	59	0	0
T73	0	29	0	0
T74	0	317	0	0
T75	0	510	0	0
T84	0	30	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12479	0	0
T2	8030	72	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	266	0	0
T43	0	8	0	0
T44	0	167	0	0
T50	0	17	0	0
T72	0	33	0	0
T73	0	36	0	0
T74	0	316	0	0
T75	0	459	0	0
T84	0	27	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12870	0	0
T2	8030	90	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	258	0	0
T43	0	10	0	0
T44	0	155	0	0
T50	0	16	0	0
T72	0	57	0	0
T73	0	29	0	0
T74	0	260	0	0
T75	0	455	0	0
T84	0	34	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	12809	0	0
T2	8030	90	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	224	0	0
T43	0	16	0	0
T44	0	170	0	0
T50	0	7	0	0
T72	0	53	0	0
T73	0	27	0	0
T74	0	281	0	0
T75	0	446	0	0
T84	0	31	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6975	0	0
T2	8030	20	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	87	0	0
T43	0	1	0	0
T44	0	30	0	0
T50	0	1	0	0
T74	0	121	0	0
T75	0	310	0	0
T84	0	12	0	0
T88	0	523	0	0
T89	0	82	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	7106	0	0
T2	8030	10	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	81	0	0
T44	0	45	0	0
T50	0	11	0	0
T74	0	137	0	0
T75	0	326	0	0
T84	0	20	0	0
T88	0	506	0	0
T89	0	115	0	0
T107	0	3	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6897	0	0
T2	8030	16	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	63	0	0
T44	0	37	0	0
T50	0	6	0	0
T74	0	108	0	0
T75	0	287	0	0
T84	0	23	0	0
T88	0	500	0	0
T89	0	112	0	0
T107	0	3	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6878	0	0
T2	8030	23	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	69	0	0
T43	0	4	0	0
T44	0	47	0	0
T50	0	5	0	0
T74	0	93	0	0
T75	0	333	0	0
T84	0	27	0	0
T88	0	465	0	0
T107	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6692	0	0
T2	8030	18	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	56	0	0
T44	0	38	0	0
T50	0	12	0	0
T74	0	121	0	0
T75	0	280	0	0
T84	0	37	0	0
T88	0	455	0	0
T89	0	110	0	0
T107	0	16	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6878	0	0
T2	8030	14	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	73	0	0
T43	0	9	0	0
T44	0	29	0	0
T50	0	6	0	0
T74	0	147	0	0
T75	0	375	0	0
T84	0	8	0	0
T88	0	469	0	0
T107	0	7	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6722	0	0
T2	8030	15	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	52	0	0
T43	0	3	0	0
T44	0	24	0	0
T50	0	4	0	0
T74	0	141	0	0
T75	0	290	0	0
T84	0	17	0	0
T88	0	394	0	0
T107	0	4	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12944564	6759	0	0
T2	8030	27	0	0
T3	26423	0	0	0
T4	3949	0	0	0
T5	53599	0	0	0
T6	3974	0	0	0
T7	2275	0	0	0
T8	26047	0	0	0
T9	28224	0	0	0
T10	41621	0	0	0
T12	1314	0	0	0
T23	0	79	0	0
T43	0	9	0	0
T44	0	23	0	0
T50	0	7	0	0
T74	0	151	0	0
T75	0	350	0	0
T84	0	25	0	0
T88	0	450	0	0
T89	0	98	0	0