Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605813	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

366032

1

T1

1133

T2

2

T3

3543

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	516998	1			T1	1500		T3	5234		T4	1500
values[0x0]	226859	1			T1	875		T2	2		T3	2182
values[0x1]	227988	1			T1	825		T2	2		T3	2236

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	508273	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

463572

1

T1

1444

T2

2

T3

4560

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3538	1			T1	9		T3	38		T6	4
valid_sources[0x01]	3300	1			T1	6		T3	32		T6	8
valid_sources[0x02]	2630	1			T3	36		T6	10		T21	16
valid_sources[0x03]	3425	1			T3	40		T6	8		T21	14
valid_sources[0x04]	4532	1			T1	30		T3	30		T6	12
valid_sources[0x05]	6352	1			T1	24		T3	39		T6	15
valid_sources[0x06]	3024	1			T1	19		T3	46		T6	11
valid_sources[0x07]	3036	1			T3	36		T6	21		T20	140
valid_sources[0x08]	4002	1			T1	20		T3	37		T6	10
valid_sources[0x09]	3539	1			T1	27		T3	41		T6	3
valid_sources[0x0a]	3943	1			T1	9		T3	50		T6	9
valid_sources[0x0b]	4170	1			T1	4		T3	37		T6	24
valid_sources[0x0c]	3731	1			T3	41		T6	16		T21	8
valid_sources[0x0d]	3217	1			T3	34		T6	21		T21	12
valid_sources[0x0e]	3581	1			T3	34		T6	12		T21	13
valid_sources[0x0f]	3908	1			T1	49		T3	33		T6	20
valid_sources[0x10]	3863	1			T1	16		T3	37		T6	19
valid_sources[0x11]	3862	1			T1	54		T3	41		T6	1
valid_sources[0x12]	3131	1			T1	4		T3	30		T6	11
valid_sources[0x13]	3615	1			T1	8		T3	22		T9	1
valid_sources[0x14]	4080	1			T1	51		T3	37		T6	13
valid_sources[0x15]	2907	1			T1	1		T3	32		T6	5
valid_sources[0x16]	4129	1			T1	17		T3	39		T6	13
valid_sources[0x17]	3659	1			T1	27		T3	33		T6	14
valid_sources[0x18]	3451	1			T1	21		T3	35		T6	20
valid_sources[0x19]	4339	1			T1	21		T3	33		T6	22
valid_sources[0x1a]	4021	1			T1	6		T3	41		T6	12
valid_sources[0x1b]	3387	1			T1	5		T3	42		T6	12
valid_sources[0x1c]	3452	1			T1	3		T3	38		T6	9
valid_sources[0x1d]	3291	1			T1	24		T3	35		T6	9
valid_sources[0x1e]	3833	1			T1	6		T3	26		T6	19
valid_sources[0x1f]	3953	1			T3	39		T6	11		T7	3
valid_sources[0x20]	3356	1			T1	13		T3	37		T6	24
valid_sources[0x21]	4269	1			T1	12		T3	30		T6	17
valid_sources[0x22]	3999	1			T1	24		T3	29		T6	12
valid_sources[0x23]	4388	1			T1	6		T3	35		T6	10
valid_sources[0x24]	3223	1			T1	25		T3	41		T6	3
valid_sources[0x25]	8577	1			T1	21		T3	26		T6	17
valid_sources[0x26]	4409	1			T1	19		T3	30		T6	10
valid_sources[0x27]	3745	1			T1	8		T3	45		T6	7
valid_sources[0x28]	3592	1			T1	12		T3	37		T6	16
valid_sources[0x29]	4084	1			T3	36		T6	7		T20	112
valid_sources[0x2a]	7421	1			T1	12		T3	34		T6	8
valid_sources[0x2b]	2928	1			T1	37		T3	41		T6	5
valid_sources[0x2c]	3346	1			T1	1		T3	49		T6	6
valid_sources[0x2d]	3916	1			T1	11		T3	35		T6	6
valid_sources[0x2e]	3473	1			T3	31		T6	2		T21	5
valid_sources[0x2f]	3285	1			T1	49		T3	35		T6	16
valid_sources[0x30]	3260	1			T1	28		T3	30		T6	8
valid_sources[0x31]	3056	1			T1	12		T3	36		T6	10
valid_sources[0x32]	4624	1			T3	34		T21	15		T23	36
valid_sources[0x33]	4408	1			T3	35		T6	11		T21	12
valid_sources[0x34]	6503	1			T1	7		T3	43		T6	14
valid_sources[0x35]	3097	1			T3	30		T6	22		T21	9
valid_sources[0x36]	3519	1			T1	31		T3	33		T6	2
valid_sources[0x37]	4102	1			T3	39		T6	10		T21	16
valid_sources[0x38]	3227	1			T3	35		T6	16		T21	11
valid_sources[0x39]	3151	1			T3	45		T6	4		T9	3
valid_sources[0x3a]	3955	1			T3	29		T6	25		T21	13
valid_sources[0x3b]	3791	1			T1	11		T3	43		T6	14
valid_sources[0x3c]	3465	1			T1	25		T3	40		T6	22
valid_sources[0x3d]	3649	1			T1	1		T3	32		T6	14
valid_sources[0x3e]	3034	1			T3	42		T6	23		T7	1
valid_sources[0x3f]	3278	1			T1	15		T3	35		T6	12
valid_sources[0x40]	4556	1			T3	38		T6	15		T9	25
valid_sources[0x41]	3431	1			T1	14		T3	34		T6	6
valid_sources[0x42]	3687	1			T3	50		T6	10		T9	10
valid_sources[0x43]	3740	1			T3	36		T6	19		T21	13
valid_sources[0x44]	3866	1			T3	28		T6	13		T21	12
valid_sources[0x45]	5014	1			T1	18		T3	29		T6	5
valid_sources[0x46]	2874	1			T1	7		T3	33		T6	20
valid_sources[0x47]	3502	1			T3	42		T6	15		T21	9
valid_sources[0x48]	3624	1			T1	3		T3	36		T6	10
valid_sources[0x49]	2792	1			T3	42		T6	12		T10	1
valid_sources[0x4a]	3080	1			T1	57		T3	33		T6	15
valid_sources[0x4b]	3008	1			T3	45		T6	12		T21	8
valid_sources[0x4c]	4092	1			T1	14		T3	32		T6	10
valid_sources[0x4d]	3639	1			T1	20		T3	37		T6	13
valid_sources[0x4e]	3129	1			T1	18		T3	43		T6	7
valid_sources[0x4f]	3521	1			T1	31		T3	54		T6	5
valid_sources[0x50]	2993	1			T1	5		T3	39		T6	14
valid_sources[0x51]	4051	1			T1	66		T3	34		T6	12
valid_sources[0x52]	4026	1			T1	22		T3	35		T6	11
valid_sources[0x53]	6694	1			T1	6		T3	48		T6	3
valid_sources[0x54]	3694	1			T1	2		T3	46		T6	16
valid_sources[0x55]	2842	1			T1	13		T3	50		T6	4
valid_sources[0x56]	4315	1			T1	31		T3	28		T6	6
valid_sources[0x57]	4019	1			T3	40		T6	12		T20	70
valid_sources[0x58]	3180	1			T3	38		T6	18		T21	10
valid_sources[0x59]	5108	1			T2	1		T3	38		T6	14
valid_sources[0x5a]	3950	1			T1	3		T3	31		T6	11
valid_sources[0x5b]	2940	1			T1	48		T3	42		T6	14
valid_sources[0x5c]	3938	1			T3	38		T6	7		T21	9
valid_sources[0x5d]	3245	1			T1	6		T3	33		T6	15
valid_sources[0x5e]	2971	1			T3	38		T6	12		T21	14
valid_sources[0x5f]	3356	1			T1	14		T3	29		T6	13
valid_sources[0x60]	3276	1			T1	1		T3	34		T6	25
valid_sources[0x61]	3416	1			T1	20		T3	39		T6	6
valid_sources[0x62]	3144	1			T1	21		T3	41		T6	14
valid_sources[0x63]	3777	1			T3	30		T6	6		T21	16
valid_sources[0x64]	4121	1			T3	45		T6	16		T21	9
valid_sources[0x65]	3268	1			T3	47		T6	13		T21	14
valid_sources[0x66]	3457	1			T1	15		T3	37		T6	16
valid_sources[0x67]	3490	1			T1	7		T3	37		T6	28
valid_sources[0x68]	4001	1			T1	7		T3	47		T6	4
valid_sources[0x69]	4670	1			T3	35		T6	7		T21	23
valid_sources[0x6a]	4434	1			T1	30		T3	44		T6	16
valid_sources[0x6b]	3605	1			T3	42		T6	20		T21	17
valid_sources[0x6c]	3498	1			T3	44		T6	14		T21	14
valid_sources[0x6d]	4257	1			T1	27		T3	45		T6	12
valid_sources[0x6e]	4388	1			T1	12		T3	32		T6	5
valid_sources[0x6f]	3326	1			T1	7		T3	55		T6	9
valid_sources[0x70]	3512	1			T3	30		T6	27		T11	1
valid_sources[0x71]	3062	1			T1	19		T3	40		T6	21
valid_sources[0x72]	5340	1			T3	37		T6	12		T8	379
valid_sources[0x73]	4201	1			T1	15		T3	30		T6	11
valid_sources[0x74]	3402	1			T1	17		T3	41		T6	20
valid_sources[0x75]	2885	1			T3	50		T6	15		T21	11
valid_sources[0x76]	3508	1			T1	78		T3	35		T6	4
valid_sources[0x77]	3230	1			T3	30		T6	1		T21	11
valid_sources[0x78]	3295	1			T3	40		T6	16		T21	6
valid_sources[0x79]	3252	1			T1	1		T3	39		T6	11
valid_sources[0x7a]	6804	1			T1	30		T3	45		T6	8
valid_sources[0x7b]	3240	1			T1	10		T3	38		T6	4
valid_sources[0x7c]	3580	1			T3	40		T6	12		T21	18
valid_sources[0x7d]	3511	1			T1	15		T3	38		T6	11
valid_sources[0x7e]	3922	1			T1	19		T3	47		T6	1
valid_sources[0x7f]	3767	1			T1	18		T3	35		T6	16
valid_sources[0x80]	3324	1			T3	47		T6	14		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

242975

1

T1

683

T3

2450

T4

695

values[0x0]

all_enables

biggest_size

80397

1

T1

299

T2

2

T3

730

values[0x1]

all_enables

biggest_size

42660

1

T1

151

T3

363

T4

131