Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	10695508	13029	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	10695508	120284	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	10695508	6431014	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	10695508	192103	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	10695508	13029	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	10695508	120284	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	10695508	6431014	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	10695508	192103	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	13029	0	0
T1	26023	75	0	0
T2	1211	0	0	0
T3	60997	131	0	0
T4	42338	75	0	0
T5	4498	0	0	0
T6	42063	75	0	0
T7	1838	0	0	0
T8	5986	4	0	0
T9	4425	4	0	0
T10	4028	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	90	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	120284	0	0
T1	26023	702	0	0
T2	1211	0	0	0
T3	60997	1192	0	0
T4	42338	713	0	0
T5	4498	0	0	0
T6	42063	702	0	0
T7	1838	0	0	0
T8	5986	38	0	0
T9	4425	37	0	0
T10	4028	0	0	0
T20	0	273	0	0
T21	0	335	0	0
T22	0	38	0	0
T23	0	819	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	6431014	0	0
T1	26023	8726	0	0
T2	1211	596	0	0
T3	60997	31763	0	0
T4	42338	24954	0	0
T5	4498	841	0	0
T6	42063	24834	0	0
T7	1838	1197	0	0
T8	5986	5040	0	0
T9	4425	3485	0	0
T10	4028	594	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	192103	0	0
T1	26023	1126	0	0
T2	1211	0	0	0
T3	60997	1917	0	0
T4	42338	1106	0	0
T5	4498	0	0	0
T6	42063	1116	0	0
T7	1838	0	0	0
T8	5986	62	0	0
T9	4425	61	0	0
T10	4028	0	0	0
T20	0	459	0	0
T21	0	502	0	0
T22	0	67	0	0
T23	0	1319	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	13029	0	0
T1	26023	75	0	0
T2	1211	0	0	0
T3	60997	131	0	0
T4	42338	75	0	0
T5	4498	0	0	0
T6	42063	75	0	0
T7	1838	0	0	0
T8	5986	4	0	0
T9	4425	4	0	0
T10	4028	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	90	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	120284	0	0
T1	26023	702	0	0
T2	1211	0	0	0
T3	60997	1192	0	0
T4	42338	713	0	0
T5	4498	0	0	0
T6	42063	702	0	0
T7	1838	0	0	0
T8	5986	38	0	0
T9	4425	37	0	0
T10	4028	0	0	0
T20	0	273	0	0
T21	0	335	0	0
T22	0	38	0	0
T23	0	819	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	6431014	0	0
T1	26023	8726	0	0
T2	1211	596	0	0
T3	60997	31763	0	0
T4	42338	24954	0	0
T5	4498	841	0	0
T6	42063	24834	0	0
T7	1838	1197	0	0
T8	5986	5040	0	0
T9	4425	3485	0	0
T10	4028	594	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	192103	0	0
T1	26023	1126	0	0
T2	1211	0	0	0
T3	60997	1917	0	0
T4	42338	1106	0	0
T5	4498	0	0	0
T6	42063	1116	0	0
T7	1838	0	0	0
T8	5986	62	0	0
T9	4425	61	0	0
T10	4028	0	0	0
T20	0	459	0	0
T21	0	502	0	0
T22	0	67	0	0
T23	0	1319	0	0